XL-30H/30W
– 48 –
IC802 VHiTC9462F/-1: Servo/Signal Control (TC9462F) (1/3)
1*
TEST0
Input
Test mode terminal. To be opened usually.
2*
/HSO
Output
Playback speed mode flag output terminal.
3*
/UHSO
Output
4*
EMPH
Output
Sub-code Q data emphasis flag output terminal. "H": Emphasis ON "L": Emphasis OFF
The output polarity can be inverted by command.
5*
LRCK
Output
Channel clock (44.1 kHz) output terminal. "L": L channel "H": R channel
The output polarity can be inverted by command.
6
VSS
—
Digital ground terminal.
7*
BCK
Output
Bit clock (1.4122 MHz) output terminal.
8*
AOUT
Output
Audio data output terminal.
9*
DOUT
Output
Digital out output terminal.
10*
MBOV
Output
Buffer memory over signal output terminal. "H": Over
11*
IPF
Output
Correction flag output terminal.
"H": When AOUT output is correction-disabled symbol in case of C2 correction output.
12*
SBOK
Output
Sub-code Q data CRCC judgment result output terminal. "H": When judgment result is OK.
13*
CLCK
Input/Output
Sub-code P-W data read clock output/input terminal. Selectable with command bit.
14
VDD
—
D power terminal.
15
VSS
—
Digital ground terminal.
16*
DATA
Output
Sub-code P-W data output terminal.
17*
SFSY
Output
Playback system frame sync signal output terminal.
18*
SBSY
Output
Sub-code block sync output terminal. "H": On S1 position when the sub-code sync is detected.
19*
SPCK
Output
Processor status signal read clock (176.4 kHz) output terminal.
20*
SPDA
Output
Processor status signal output terminal.
21*
COFS
Output
Correction system frame clock (7.35 kHz) output terminal.
22*
MONIT
Output
LSI internal signal monitor terminal.
It is possible to monitor the DSP internal flag and PLL system clock with the microcomputer
command. Terminal for serial output of text data according to command .
23
VDD
—
D power terminal.
24
TESIO0
Input
Test input/output terminal. To be fixed to "L" usually.
Terminal to input the text data read clock according to command.
25
P2VREF
—
2VREF terminal for PLL system.
26*
HSSW
Output
VREF voltage in case of x2 speed/x4 speed.
27*
ZDET
Output
1-bit DAC zero detection flag output terminal.
28
PDO
Output
Terminal to output the phase difference between EFM signal and PLCK signal.
29*
TMAXS
Output
TMAX detection result output terminal. To be selected with command bit TMPS.
30
TMAX
Output
TMAX detection result output terminal. To be selected with command bit TMPS.
31
LPFN
Input
Low-pass filter amp inverted input terminal.
32
LPFO
Output
Low-pass filter amp output terminal.
33
PVREF
—
VREF terminal for PLL system.
34
VCOREF
Input
VCO center frequency standard level terminal. To be fixed to PVref usually.
35
VCOF
Output
VCO filter terminal.
36
AVSS
—
Analog system ground terminal.
37
SLCO
Output
Data slice level generation DAC output terminal.
38
RFI
Input
RF signal input terminal.
Pin No.
Port Name
Function
Input/Output
H
H
x1 speed playback
H
L
x2 speed playback
L
H
x4 speed playback
L
L
—
/UHSO
/HSO
Playback speed
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Longer than specific period
"P2VREF"
Shorter than specific period
"VSS"
Within specific period
"HIZ"
TMAX detection result
TMAX output
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