Date Code 20001006
Inputs, Outputs, Timers, and Other Control Logic
7-19
SEL-351 Instruction Manual
Figure 7.17: Time Line for Reset of Latch Bit LT2 After Active Setting Group Change
In Figure 7.17, latch bit LT2 is reset (deasserted to logical 0) when reset setting RST2 asserts to
logical 1 for the short time right after setting Group 4 is activated. This logic can be repeated for
other latch bits.
Note: Make Latch Control Switch Settings With Care
The latch bit states are stored in nonvolatile memory so they can be retained during power loss,
settings change, or active setting group change. The nonvolatile memory is rated for a finite
number of “writes” for all cumulative latch bit state changes. Exceeding the limit can result in an
EEPROM self-test failure. An average of 150 cumulative latch bit state changes per day can be
made for a 25 year relay service life.
This requires that SEL
OGIC
Control Equation settings SETn and RSTn for any given latch bit LTn
(n = 1 through 8; see Figure 7.13) be set with care. Settings SETn and RSTn cannot result in
continuous cyclical operation of latch bit LTn. Use timers to qualify conditions set in settings
SETn and RSTn. If any optoisolated inputs IN1 through IN8 are used in settings SETn and RSTn,
the inputs have their own debounce timer that can help in providing the necessary time qualification
(see Figure 7.1).
In the preceding reclosing relay enable/disable example application (Figure 7.15 and Figure 7.16),
the SCADA contact cannot be asserting/deasserting continuously, thus causing latch bit LT1 to
change state continuously. Note that the rising edge operators in the SET1 and RST1 settings keep
latch bit LT1 from cyclically operating for any single assertion of the SCADA contact.
Содержание SEL-351
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