
-96-
60
D0
D0
Data Bus
-
I/O
61
A0
A0
Address Bus
-
O
62
A1
A1
Address Bus
-
O
63
A2
A2
Address Bus
-
O
64
VssQ
GND
Vss for I/O (0V)
-
-
65
A3
A3
Address Bus
-
O
66
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
67
A4
A4
Address Bus
-
O
68
A5
A5
Address Bus
-
O
69
A6
A6
Address Bus
-
O
70
A7
A7
Address Bus
-
O
71
A8
A8
Address Bus
-
O
72
A9
A9
Address Bus
-
O
73
A10
A10
Address Bus
-
O
74
A11
A11
Address Bus
-
O
75
VssQ
GND
Vss for I/O (0V)
-
-
76
A12
A12
Address Bus
-
O
77
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
78
A13
A13
Address Bus
-
O
79
A14
A14
Address Bus
-
O
80
A15
A15
Address Bus
-
O
81
A16
A16
Address Bus
-
O
82
A17
A17
Address Bus
-
O
83
A18
A18
Address Bus
-
O
84
A19
A19
Address Bus
-
O
85
A20
A20
Address Bus
-
O
86
VssQ
GND
Vss for I/O (0V)
-
-
87
A21
A21
Address Bus
-
O
88
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
89
A22
A22
Address Bus
-
O
90
A23
A23
Address Bus
-
O
91
Vss
GND
Vss (0V)
-
-
92
A24
A24
Address Bus
-
O
93
Vcc
1.9V
Vcc (1.9V)
-
-
94
A25
A25
Address Bus
-
O
95
BS/PTK[4]
BS [for ICE]
Bus Cycle Starting Signal
O
96
RD
RD
Read Strobe
O
97
WE0/DQMLL
WE0
D7-D0 Select Signal / DQM (SDRAM)
O
98
WE1/DQMLU/WE
WE1
D15-D8 Select Signal / DQM (SDRAM)
O
99
WE2/DQMUL/ICIORD/PTK[6]
WE2
D23-D16 Select Signal / DQM (SDRAM)
O
100
VssQ
GND
Vss for I/O (0V)
-
-
101
WE3/DQMUU/ICIOWR/PTK[7]
WE3
D31-D24 Select Signal / DQM (SDRAM)
O
102
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
103
RD/WR
RDWR
Read / Write
O
104
PTE[7]/PCC0RDY/AUDSYNC
AUDSYNC [for ICE] AUD_SYNC
O
105
CS0
CS0
Chip Select_0 Flash Memory [32bit]
O
106
CS2
CS2
Chip select_2 Peripheral Device_1 [16bit]
O
107
CS3
CS3
Chip select_3 SDRAM [32bit]
O
108
CS4/PTK[2]
CS4
Chip select_4 Peripheral Device_2 [8bit]
O
109
CS5/CE1A/PTK[3]
CS5
Chip select_5 Peripheral Device_3 [32bit]
O
110
CS6/CE1B
(Reserve)
Chip select_6
(Open)
-
111
CE2A/PTE[4]
(Reserve)
Area_5 PCMCIA Card Enable / I/O Port_E
(Open)
-
112
CE2B/PTE[5]
(Reserve)
Area_6 PCMCIA Card Enable / I/O Port_E
(Open)
-
113
AFE_Hc1/USB1d_Dpls/Ptk[0]
AFE Hardware Control / D+ Input / I/O Port_K
(Open)
-
114
AFE_Rly/USB1d_Dmns/Ptk[1]
AFE Relay Control / D- Input / I/O Port_K
(Open)
-
115
VssQ
GND
Vss for I/O (0V)
-
-
116
AFE_SCLK/USB1d_TXDPLS
AFE Clock / D+ Output
(Pull-up)
-
117
VccQ
3.3V
Vcc for I/O (3.3V)
-
-
118
Ptm7/Pint7/Afe_FS/USB_RCV
Port_M / Port Interrupt / AFE Frame Sync / Receiver (Open)
-
119
Ptm6/Pint6/Rxin/USB_Speed
Port_M / Port Interrupt / AFE Receiver / Speed Control
(Open)
-
120
Ptm5/Pint5/Txo/USB_Txse0
Port_M / Port Interrupt / AFE Transceiver / SE0 State (Open)
-
Pin No.
Name
Function Name
Function
Polarity
I/O
Control Port Functions
Содержание PLV-HD10
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Страница 107: ... 107 M62420 Audio Control IC5003 PW365 Scan Converter IC301 IC Block Diagrams ...
Страница 108: ... 108 Sii169ACT DVI Interface IC8001 TA1318N Sync Separator Frequency Counter IC1061 IC Block Diagrams ...
Страница 116: ... 116 70 84 84 84 84 72 73 71 93 94 97 98 96 95 62 Fig 89 Fig 90 ...
Страница 119: ... 119 114 115 102 103 114 119 118 122 121 113 112 117 Fig 95 Mirrors Fig 96 Lenses ...
Страница 154: ...Memo ...
Страница 155: ...Memo ...
Страница 156: ...SANYO Electric Co Ltd Oct 2003 Printed in japan ...
Страница 178: ...Diagrams Drawings M4MA ...