5
CIRCUIT OPERATIONAL DESCRIPTION
DQ0
DQ15
UDQM
LDQM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE:
The cell array configuration is 4096 * 256 * 16
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
R
E
D
O
C
E
D
W
O
R
A0
A9
BS0
BS1
CS
RAS
CAS
WE
A11
SDROM PT48046TG-70 Block Diagram
Sm(SANYO_DVD-DX500)051220.indd 15
2005-12-29 8:58:46
Содержание DVD-DX500
Страница 19: ...18 CIRCUIT DIAGRAM 1 POWER SUPPLY SCHEMATIC DIAGRAM Sm SANYO_DVD DX500 051220 indd 18 2005 12 29 8 58 49 ...
Страница 21: ...CIRCUIT DIAGRAM 20 2 RF MPEG SCHEMATIC DIAGRAM Sm SANYO_DVD DX500 051220 indd 20 2005 12 29 8 58 54 ...
Страница 22: ...CIRCUIT DIAGRAM 21 3 SDRAM FLASH SCHEMATIC DIAGRAM Sm SANYO_DVD DX500 051220 indd 21 2005 12 29 8 58 58 ...
Страница 23: ...CIRCUIT DIAGRAM 22 4 VIDEO OUTPUT PORT SCHEMATIC DIAGRAM Sm SANYO_DVD DX500 051220 indd 22 2005 12 29 8 59 01 ...
Страница 24: ...CIRCUIT DIAGRAM 23 5 AUDIO OUTPUT PORT SCHEMATIC DIAGRAM Sm SANYO_DVD DX500 051220 indd 23 2005 12 29 8 59 04 ...
Страница 25: ...CIRCUIT DIAGRAM 24 3 CONTROL BOARD SCHEMATIC DIAGRAM Sm SANYO_DVD DX500 051220 indd 24 2005 12 29 8 59 07 ...
