CP3005 – User Guide Rev. 1.8
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Bitfield
Description
11 = COMA, COMB
3 - 0
MEZC
Mezzanine configuration:
0000 = None/Smart Extension Module
0001 = MMEXT-XMC02 extension module
0010 = MMEXT05 extension module
0011...FFFF = Reserved
*The default value depends on the CP3005 version ordered (front I/O or rear I/O) and the rear I/O module used.
4.3.9.
Board ID High-Byte Register (BIDH)
Table 27: Board ID High-Byte Register (BIDH)
Address
0x288
Bit
7
6
5
4
3
2
1
0
Name
BIDH
R
0xB4
Access
Reset
Bitfield
Description
7 - 0
BIDH
Board identification:
CP3005: 0xB480
The Board ID Low Byte Register is located at the address 0x28D.
4.3.10.
Board and PLD Revision Register (BREV)
The Board and PLD Revision Register signals to the software when differences in the board and the Programmable
Logic Device (PLD) require different handling by the software. It starts with the value 0x00 and will be incremented
with each necessary change.
Table 28: Board and PLD Revision Register (BREV)
Address
0x289
Bit
7
6
5
4
3
2
1
0
Name
BREV
PREV
Access
R
R
Reset
N/A
N/A
Bitfield
Description
7 - 4
BREV
Board revision
3 - 0
PREV
PLD revision