Samsung VP-D455, Руководство по обслуживанию

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Circuit Operating Description
Samsung Electronics 13-9
13-3-5 PRML Block H/W Function Specifications
PRML BLOCK performs the data control in each mode using MICOM’s Control Signal. After Head S/W
Pulse is input, it can also consecutively process the signal by separating the high-interval and low-interval
signals of the envelope output during playback.
Receiving the control signal from DV-1 chip, it should be controlled to stop operating (Power Down) during
the REC Time and to process signals normally during the PB Time. Also, it should also be able to perform
playback by providing a 41.85MHz PB Clock and PB Data to the DV-1 chip. Supplied with a 41.85 MHz
signal (or 54 MHz from DSP6) from the DV-1 Chip, it should stably play back by switching the signal to PB
Clock when an unstable signal is received from the PREAMP.
It supplies 41.85 Mbps PB data to the DV-1 Chip after being provided with the playback output signal from
the Differential input (DIP, DIN) of the PREAMP. It also provides a 41.85 MHz PB Clock to the DV-1 Chip by
doubling the 20.925MHz (X2) which is the highest frequency of the playback signal.
It produces an ATF Error Signal from the playback output signal and gives the signal to MICOM Block so
that it can be used as the Capstan Control. It takes two kinds of voltage, 3Vdc and 1.8Vdc from DC/DC and
uses them for internal operating voltage and the reference voltage of this block which is used for controlling
the signal that connects with the exterior. It can also operate the internal 1.8V regulator with an external
option (pull up or pull down). In this case, it can operate at one external operating voltage of 3V.