Circuit Description
5-2
SF700AT
Figure 5-2: XFC-B Hardware Interface Signals
5-2-2 Data & Address Bus Control
/RD and /WR signals are active in the low state,
with the PH2 clock in a high state, and an internal
wait state occurs in the TSTCLK (6 MHz). These
signals are sent to the /RD and /WR ports of
RAM , ROM, and the MODEM in order to read or
write data when a chip select line is active.
/CS0: RAM chip select active (low)
/ROMCS: ROM chip select active (low)
/MCS: MODEM chip select active (low)
D0 - D7: 8 bit data bus
A0 - A16: address bus
5-2-3 System Clock
The 6 MHz internal clock frequency is generated
by dividing the 12 MHz system clock from
MODEM by two inside the MODEM.
OPERATOR
PANEL
SERIAL
COMMUNICATION
PRINTER
DATA
CONTROL
AND
SENSORS
MOTOR
DRIVER
(MOTOR)
SCANNER
CONTROL
AND
PROCESSING
RTC
CRYSTAL
EXTERNAL
BUS
MODEM
GENERAL
PURPOSE
I/ 0
TXD
RXD
STB 0~3
PDAT
PCLK
PLAT
THADI
SM 0~3
MOTOR POS
START
SCLK
VIDCTL1
H/B
Vin
+Vref
-Vref
XIN
XOUT
/ROMCS
/RAMCS
/RD/WR
D0~D7
A0~A16
/RD/WR
D0~D7
A0~A4
/MCS
/MIRQ
SYSCLK
/PWRDWN
/RESET
/BATRST
IFC(XFC-B)
Содержание SF700AT
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