100BASE-TX ANALOG BLOCKS
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
6-8
Preliminary Spec. ver
1.4
line termination is performed by the circuit shown in Figure 6-5.
RECEIVE CLOCK RECOVERY(20MHZ,DPLL)
An on-chip frequency synthesis PLL recovers a 20MHz clock using the frequency reference from receiving data.
The PLL uses digital techniques to create the optimum clock for re-timinig the received data.
Содержание KS8910
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Страница 4: ...PRELIMINARY SPECIFICATION vi KS8910 100 10 Mbps ETHERNET CONTROLLER ...
Страница 21: ...EXTERNAL SIGNALS KS8910 100 10 Mbps ETHERNET TRANSCEIVER 2 8 Preliminary Spec ver 1 4 MEMO ...
Страница 47: ...10BASE T DIGITAL BLOCKS KS8910 100 10 Mbps ETHERNET TRANSCEIVER 5 6 Preliminary Spec ver 1 4 MEMO ...
Страница 89: ...APPLICATION NOTE KS8910 100 10 Mbps ETHERNET TRANSCEIVER 9 2 Preliminary Spec ver 1 4 MEMO ...
Страница 91: ...MECHANICAL DATA KS8910 100 10 Mbps ETHERNET TRANSCEIVER 10 2 Preliminary Spec ver 1 4 MEMO ...
Страница 99: ...A 8 APPENDIX KS8910 100 10 Mbps ETHERNET TRANSCEIVER Preliminary Spec ver 1 4 NOTES ...