Renesas 8V19N850, Руководство пользователя

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8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021 Page 4
1. Determine desired loop bandwidth fc. The fc must satisfy the following condition:
20
>>
fc
Fpd
Where, Fpd is phase detector input frequency.
2. Calculate Rs
𝑅𝑅𝑅𝑅 =
2 ∗
π
∗ fc ∗ N
Icp ∗ Kvco
Where,
Icp is charge pump current.
Kvco is VCO gain.
N is effective feedback divider.
Fpd
Fvco
N
=
Fvco is vco frequency.
Fpd is the phase detector input frequency.
3. Calculate Cs
𝐶𝐶𝑅𝑅 =
α
2 ∗ 𝜋𝜋 ∗ 𝑓𝑓𝑓𝑓 ∗ 𝑅𝑅𝑓𝑓
Where,
α is ratio between loop bandwidth and the zero frequency at zero, α
= fc / fz,
recommend α greater than 3
.
fz is frequency at zero.
4. Calculate Cp
𝐶𝐶𝐶𝐶 =
Cs
α ∗ β
Where,
β
is ratio between frequency at pole and loop bandwidth,
β = fp
/
fc, recommend β greater than 3
.
fp is frequency at pole.
5. Verify maximum Phase Margin, PM
)
* 2
1
arctan(
b
b
PM
−
=
Where,
b = 1 +
𝐶𝐶𝑅𝑅
𝐶𝐶𝐶𝐶
PM should be greater than 50 degrees.