8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 3
To minimize ESR between power pins and the bypass capacitors, it is recommended to place at least one
bypass capacitor at each VDD power pin, with a placement as near as possible to the respective power pin of
the device. A thick trace width between the bypass capacitor and power pin helps to reduce ESR. It is
recommended to combine multiple capacitors at different resonance frequencies to achieve band pass filter
characteristics at the critical noise frequencies.
1.2
Power Supply Isolation
The power rails should be as noise-free as possible to support the low phase noise performance of the device
PLLs. The 8V19N850 also integrates LDOs for additional noise filtering. An external ultra-low noise LDO may not
be required but it is recommended for further reducing power supply noise. An LDO should have a noise level of
less than 6.5uVrms from 10Hz to100kHz. The Renesas RAA214020 is a suitable LDO.
It is recommended to isolate the analog power rail from other high noise power rails, VDDO_x and VDD_INPUT.
The isolation can be implemented through an RC low pass filter. The larger RC component values can further
reduce the cutoff frequency and clean up lower frequency noise. For the output supplies VDDO_x, to reduce
output frequency interference, the power rails between the output banks that operate at different output
frequencies can be isolated using separate LDOs or using 1 to 2 ohm resistors if they share the same power
source. Additional smaller value capacitors (e.g., 100pF) in parallel with the existing 0.1µF near the power pins
can provide additional higher frequency noise filtering.
1.3
Loop Filter
1.4
2
nd
Order Loop Filter
The 8V19N850 contains four Analog PLLs: APLL0, APLL1, APLL2, and RFPLL. These analog PLLs require
board-level 2
nd
order loop filter. The approximate VCO frequency and VCO gains for each APLL is displayed in
Table 1. The VCO gain Kvco depend on the operating region.
Table 1. 2
nd
Order Loop Filter
APLL
Approximate VCO
Frequency (GHz)
Kvco (MHz/V)
APLL0
2.5
30
APLL1
3.93216
48
APLL2
3.75
52
RFPLL
2.94912
38
The following section provides a general design of a 2
nd
order loop filter for PLL. A typical 2
nd
order loop filter is
shown in Figure 3. The design shows a step-by-step calculation to determine Rs, Cs, and Cp values. The
required parameters for this part are also provided. A spreadsheet or software tool for calculating the loop filter
values are also available.
Figure 3. Typical 2
nd
Order Loop Filter
Cp
Charge Pump Driv er
Rs
Loop Filter Return
Cs
