Realtek RTD2120-series
confidential
10
The Clock Control register (CKCON
–
8Eh) determines these timer speeds. When the relevant
CKCON bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. When the control
bit is set to a zero, the device uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5
selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer zero. Note that
unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls
are independent.
Memory Organization
Internal Data memory
l
256 bytes of internal RAM
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128 bytes of Special Function Register (SFR)
External Data memory
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128 bytes of External Special Function Register (XFR)
l
256 bytes of DDCRAM(128-bytex2)
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256 bytes of general purpose RAM
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32k bytes of flash for EDID data and other parameters
External Program memory
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64k bytes of flash for program memory
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The program content can not be read out unless user mass erase the flash first.
flash 0~64K
Internal RAM
Direct/Indirect
addressing
flash 64~96K
Unused
General Purpose RAM
DDC_RAM1&2
Unused
XFR
0000
7FFF
F800
F8FF
F900
F9FF
FF00
FFFF
Internal RAM
Indirect addressing
SFR
Direct addressing
Internal Data Memory
External Data Memory
0000
FFFF
External Program Memory
00
7F
80
FF
Reset
There are five reset sources in RTD2120, as described below:
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RST pin
The external reset is high active and its pulse width must be larger than 16 mcu clock cycles. The
RST pin can reset the whole chip of RTD2120.
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Low voltage reset(LVR) and power on reset(POR)
The LVR and POR monitor the power status of RTD2120. The same as external reset, the LVR
and POR will reset the whole chip of RTD2120 when triggered.
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Software reset
