Realtek RTD2120K, Руководство пользователя

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Realtek RTD2120-series
confidential 26
Name Bits Read/Write Reset State Comments
IIC_ADDR 7:1 R/W 37 IIC Slave Address to decode
CH_SEL 0 R/W 0 Channel Select
0: from ADC DDC
1: from DVI DDC
Register::IIC_sub_in 0xFF28
Name Bits Read/Write Reset State Comments
IIC_SUB_AD
DR 7:0 R 00 IIC Sub-Address Received
Register::IIC_data_in 0xFF29
Name Bits Read/Write Reset State Comments
IIC_D_IN 7:0 R 00 IIC data received
Register::IIC_data_out 0xFF2A
Name Bits Read/Write Reset State Comments
IIC_D_OUT 7:0 W 00 IIC data to be transmitted
Register::IIC_status 0xFF2B
Name Bits Read/Write Reset State Comments
A_WR_I 7 R/W 0 If ADC DDC detects a STOP condition in
write mode, this bit is set to
“
1
”
. Write 0 to
clear.
D_WR_I 6 R/W 0 If DVI DDC detects a STOP condition in
write mode, this bit is set to
“
1
”
. Write 0 to
clear.
128VS_I 5 R/W 0 In DDC2 Transition mode, SCL idle for 128
VSYNC. Write 0 to clear.
STOP_I 4 R/W 0 If IIC detects a STOP condition(slave
address must match), this bit is set to
“
1
”
.
Write 0 to clear.
D_OUT_I 3 R 0 If IIC_DATA_OUT loaded to serial-out-
byte, this bit is set to
“
1
”
. Write IIC_data_out
(FF2A) to clear.
D_IN_I 2 R 0 If IIC_DATA_IN latched, this bit is set to
“
1
”
. Read IIC_data_in (FF29) to clear.
SUB_I 1 R/W 0 If IIC_SUB latched, this bit is set to
“
1
”
Write 0 to clear.