Realtek RTD2120K, Руководство пользователя

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Realtek RTD2120-series
confidential 28
1/2
M
1/(N+1)
OSC
PLL
PWM clock generator
first stage
output
second stage
output
Register::PWM_clock_control 0xFF30
Name Bits Read/Write Reset State Comments
PWM_EN 7 R/W 0 0: Disable PWM output
1: Enable PWM output
PWM0_CK 6 R/W 0 0: Select first stage output
1: Select second stage output
PWM1_CK 5 R/W 0 0: Select first stage output
1: Select second stage output
PWM2_CK 4 R/W 0 0: Select first stage output
1: Select second stage output
PWM_CK_SE
L 3 R/W 0 PWM clock generator input source
0: Crystal
1: PLL output
reserved 2 -- 0 Reserved
PWM_M 1:0 R/W 0 PWM clock first stage divider
Register::PWM_divider_N 0xFF31
Name Bits Read/Write Reset State Comments
PWM_N 7:0 R/W 0 PWM clock Second stage divider
Register::PWM0_duty_width 0xFF32
Name Bits Read/Write Reset State Comments
PWM0_DUT 7:0 R/W 0 PWM0 duty width
Register::PWM1_duty_width 0xFF33
Name Bits Read/Write Reset State Comments
PWM1_ DUT 7:0 R/W 0 PWM1 duty width