RadiSys EXM-31, Справочник по аппаратуре

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EXM-31 Hardware Reference
Page 12
4 4
UART Registers
The table below describes the 16C550 registers.
Bit
#
Register Address
OD=0 OD=0 1D=0 2 2 3 4 5 6 7 OD
=1
1D=1
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
0 Data
bit 0
Data
bit 0 ERBFI 0 if IRQ
pend
FIFO
enable WLS0
Bit 0 DTR DR DCTS Bit 0 Bit0 Bit 8
1 Data
bit 1
Data
bit 1 ETBEI INT ID
(0)
RCVR
FIFO
reset WLS1
Bit 1 RTS OE DDSR Bit 1 Bit1 Bit 9
2 Data
bit 2
Data
bit 2 ELSI INT ID
(1)
XMIT
FIFO
reset # of
stop bits Out 1 PE TERI Bit 2 Bit2 Bit10
3 Data
bit 3
Data
bit 3 EDSSI INT ID
(2)
2
DMA
mode
select parity
enable
(PEN) Out 2 FE DDC
D Bit 3 Bit3 Bit11
4 Data
bit 4
Data
bit 4 0 0 resvd Even
Parity
Select
(EPS) Loop BI CTS Bit 4 Bit4 Bit12
5 Data
bit 5
Data
bit 5 0 0 resvd Stick
parity 0 THRE DSR Bit 5 Bit5 Bit13
6 Data
bit 6
Data
bit 6 0 FIFO
enable
2
RCVR
Trig
(LSB) Set
break 0 TEMT RI Bit 6 Bit6 Bit14
7 Data
bit 7
Data
bit 7 0 FIFO
enable
2
RCVR
Trig
(MSB) DLAB 0 RCVR
FIFO
Err
2
DCD Bit 7 Bit7 Bit15
Table 4. UART Registers.
NOTES:
1
Bit 0 is the least significant bit. It is the first bit serially transmitted or
received.
2
Interrupt ID Bit (2): These bits are always 0 in NS16450 mode