EPC-9 Hardware Reference
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Processor Module Daughterboard
An Intel Pentium processor (with integral FPU) runs at 100, 133, 166, or 200 MHz.
The processor, the TXC system controller, and the L2 cache all operate on a 66MHz
local bus. The PCIbus runs at half the local bus speed (33MHz) and the ISA bus runs
at one quarter the PCI bus speed (8.25 MHz).
Cache Memory
A second-level (L2) write-back 256KByte main-memory cache is implemented by the
Intel 82430HX chipset’s TXC system controller.
Main System Memory
Main memory is implemented as SODIMM 72-pin socketed 3.3 volt DRAM. The
main memory controller supports up to 256MB of 60 or 70 ns Fast Page Mode or
EDO DRAM in two dual 72-pin SODIMM sockets. The CPU memory bus is 64 bits
wide, so the SODIMM sockets must be populated with identical pairs of 32 bit DRAM
modules. The TXC controller generates all of the required control signals, such as
RAS#, CAS#, and WE#, as well as the multiplexed addresses for the DRAM array.
Upgrading Main System Memory
At the time of writing, the the following sizes of 60 or 70ns Fast Page Mode or EDO
DRAM were useable:
Type
Row/Column
Total Size (MB)
Number of SODIMMs
512Kx32
10/9
4
2
1Mx32
10/9 or 10/10
8
2
2Mx32
10/10 or 10/11
16
2
4Mx32
11/10, 11/11, or12/10
32
2
4Mx32
11/10, 11/11, or12/10
64
4
8Mx32
12/11
128
4
16Mx32
12/12
256
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