EPC-9 Hardware Reference
E
E
E-6
Model Register (8156h)
MODEL
8156h
This register is a write once register after reset. The intent is for the BIOS to load this
with the model number based on the EPC model. Once written, it is read only as the
low 8 bits of the device type register in the VXI register space. Hardware reset
enables writing the register again.
Signal FIFO Low (8158h)
SRFL
8158h
Signal FIFO High (8159h)
SRFH
8159h
To spell out the operation of the signal register FIFO, and associated control bits, the
operations are explained in algorithmic fashion. SIG, FSIG and LSIG are fields in the
Response register.
The signal FIFO (SRFIFO) is a two-element array with indexes. A write to the
Protocol register from the VXI bus (see VXI Register Details, below) is a write to the
signal FIFO, and does the following:
if (SIG && (FSIG != LSIG)) {
/* FIFO full */
Assert BERR
}
else {
if (SIG) LSIG = !LSIG;
SRFIFO[LSIG] = write data;
SIG = 1
}
A read from SRFL returns the low-order byte of SRFIFO(FSIG). In all cases of
accesses to SRFL and SRFH, if SIG = 0 (empty FIFO), the result is an access to
SRFIFO(0). A read from SRFH returns the high-order byte of SRFIFO(FSIG), and
does the following:
if (FSIG == LSIG) { SIG = LSIG = FSIG = 0 }
else FSIG = !FSIG;
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