EPC-9 Hardware Reference
E
E
E-10
Protocol Low Register (offset 8h)
FFh
8h
Protocol High Register (offset 9h)
1Fh
9h
A read of these registers reads the ROM constants stored in the protocol register. A
write to this register location writes the signal register.
The protocol register (the read value) defines EPC-9 as being a servant and
commander, having a signal register, being a bus master and an interrupter, not
providing the shared-memory protocol, and not providing fast handshake mode.
Response Register (offset Ah)
LOCK
RRIE
ABMH
SIG
MLK
WRC
FSIG
LSIG
Ah
Response Register (offset Bh)
0
1
DOR
DIR
ERR
RRY
WRY
1
Bh
These registers contain some VXI-defined state bits associated with message handling,
and several EPC-9 dependent bits. These registers are read-only from VME and are
read/write from the PC port. Note that some of these bits (ABMH, MLK, RRY and
WRY) can be cleared by hardware when access is made to the message registers from
the VME port. Software protocols as defined by the VXI specification guarantee that
this does not happen at the same time as a write from the PC port to these bits. If
software violates this protocol, unpredictable results will occur.
LOCK RAM bit available to software for VXI communication protocols.
RRIE
This bit is used to enable RRY interrupt signaling. When clear (reset state),
only the deassertion of WRY will cause the MSGR interrupt to be asserted.
When set, the "OR" of the deasserted RRY, WRY bits is used to assert the
interrupt.
ABMH This bit is cleared when the message high register is read or written from the
VXIbus. It serves as a location monitor for determining whether a message
is 16 or 32 bits in length.
SIG
If this bit is 0, the signal FIFO is empty.
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