Registers
E
E
E-3
Register Details
Message Registers (814Ch)
Message High Register
MH[7..0]
814Ch
Message High Register
MH[15..8]
814Dh
Message Low Register
ML[7..0]
814Eh
Message Low Register
ML[15..8]
814Fh
This is the PC-port side of the VXI message registers.
Each of the 16-bit Message registers is actually two registers, an inbound register and
an outbound register. There are actually four 16-bit locations: message high in,
message high out, message low in and message low out. Writing from the PC port
writes to the outbound register. Reading from the PC port reads the inbound register.
Writing from VME writes to the inbound register. Reading from VME reads the
outbound register.
ABMH in the Response register, described below, is cleared when the low byte of
Message High register is read or written from VME. It serves as a location monitor
for determining whether a message is 16 or 32 bits in length. Access from the PC port
has no effect on ABMH.
When the low byte of Message Low is read from VME, RRY in the Response register
is cleared. When the low byte of Message Low is written from VME, WRY in the
Response register is cleared. Access from PC port has no effect on RRY and WRY.
The low byte of Message-Low-out register is driven onto the VMEbus D[15:8] during
an IACK response cycle. VME D[7:0] is driven from the ULA register.
Control Register (8150h)
SLOT1
RONR
WDTR
WDTV
8150h
Only WDTR is cleared by a warm reset. All bits are cleared by a reset.
SLOT1
Read only bit that indicates that state of the slot1 detect.
RONR
Bus release mode. If set, the bus release mode is RONR (request on
no request); otherwise it is controlled by the bus request bits in the
Tundra Universe chip.
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