RadiSys EPC-8A, Справочник по аппаратуре

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EPC-8A Hardware Reference
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read-only.
MLCK This EPC-8A specific bit is used for synchronization of messages from
multiple senders, something not provided for in the VXI specification.
1 The message register can be locked for the sending of a message.
0 The message register is locked.
WRCP This EPC-8A specific bit is a read-only copy of the WRDY bit.
FSIG Defined only when SIG=1, in which case FSIG is the number (0 or 1) of the
register in the FIFO holding the earliest signal. This is a read-only bit.
LSIG Defined only when SIG=1, in which case LSIG is the number (0 or 1) of the
register in the FIFO holding the most recent signal. This is a read-only bit.
FSIG and LSIG have no utility to software. They exist as read-only bits for tests of
the EPC-8A during manufacture.
The protocol for sending a message to the EPC, if there are multiple potential senders, is
the following. The sender first reads register ABR (described in greater detail later). If
both WRDY and MLCK are 1, he may then proceed to send the message; if not, he must
spin or wait for this condition. For 16-bit messages, he writes into the Message Low
register.
The bits RRDY, WRDY, and MLCK in the response register are altered by
hardware-detected conditions. A read from the message-low clears RRDY. A write into all
or the lower 8 bits of the message low register clears WRDY. A read from the VME bus
port of the Alternate Bus Response register clears MLCK if WRDY is set. A read from the
Alternate Bus Response register also returns the value in the Response register. Please
note that the Alternate Bus Response register is accessed at offset 0x2A from the VME
A16 base address of these registers.
Bits MLCK, DIR, DOR, ERR can be set or cleared by using a write to the response
register from either the PC or VME ports. RRDY and WRDY may only set via a write to
the response register. For these two bits, a 0 written into the respective bit position does
not change the value of the register bit. A
1 written into the respective bit position sets the value of the register bit to 1.
Supporting software on the EPC must be aware of how to set the bits initially. Valid states
include:
RRDY WRDY MLCK State
X 1 1 Write ready (awaiting incoming msg
X 1 0 Write ready, locked by a sender
1 X X Read ready (outgoing data present)
0 0 X Not ready for write or read