RadiSys EPC-8A, Справочник по аппаратуре

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Chapter 4: Theory of Operation
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The BIOS does not enable (using bit 2 of register 8102h) the VGA controller if another
VGA controller is enabled on the EXM expansion interface.
Ethernet Controller
The EPC-8A contains an on-board Ethernet controller connected through the 16-bit EXM
expansion interface, which is compatible with Western Digital 8013, Novell NE2000 and
cards through the use of National Semiconductor’s DP83905 (AT/LANTIC
chip). The default configuration for the Ethernet port is as a WD8013-compatible card.
The I/O base address is 240. Interrupts are signaled on IRQ5. These parameters can be
changed by running the AUTOSET.EXE program, optionally available from your
supplier. The possible alternative interrupts are IRQ3, IRQ9 and IRQ15.
The EPC-8A Ethernet port has two 8 Kbytes x 8 RAM chips for packet buffering and a
10BASE-T interface. You cannot use eight-bit network drivers with the EPC-8A.
For more information about the AUTOSET.EXE program, refer to Appendix H,
AUTOSET Software.
Resident Flash/SRAM Memory
The EPC-8A can optionally be built with 2 Mbytes of Flash memory and 128 Kbytes of
Static RAM resident on the processor board.
Resident Flash Memory
The resident Flash memory is accessed via 8-bit read/write registers and physically
appears on the EXM expansion interface as if it is in slot 31. It is enabled as if it were a
standard RadiSys EXM expansion card in that slot.
The EPC returns an ID of FD to a read of address 100. This is the same ID that would be
returned from a RadiSys EXM-2A card. You can use the optional XFORMAT.EXE
utility to format and load the resident Flash memory under MS DOS. The EXM-2A and
the resident Flash memory cannot both be used in a single EPC-8A system. Note: You
must set jumper JP2 (-FLASH) before the Flash can be written. Jumper locations are
described in Figure 2-1.
SRAM
The battery-backed SRAM is memory mapped. The resident SRAM resides on the EXM
expansion interface and, when populated, can be accessed at 0xFX3XXXXX or
0xFXBXXXXX. If there is less than 16 Mbytes of DRAM, it may also be accessed at
0x00BXXXXX. A battery low indicator (low when 0) is returned in bit 0 of register 8387.
Watchdog Timer
The watchdog timer is a binary counter which, upon overflow, signals a watchdog timer
event. The counter causes a watchdog event after approximately 125 mS, 1 second or 8
seconds (depending on the value of FWDT and SWDT, bits 2 and 1 in register 815Dh) if
the application software does not reset the timer.
An I/O read to address 815Dh resets the counter. If WDTR (bit 3 of register 815Dh) is set,
the following occurs in response to a timeout event: