RadiSys EPC-8A, Справочник по аппаратуре

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Chapter 5: Programming the VMEbus Interface
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5. Set register 8130h with the value corresponding to bits 21–16 of the VMEbus address
with the two low-order bits of the register set to 0.
6. Map the address.
7. Write the data
C code for Example 2
LWORD addr; /* 32-bit A32 address */
BYTE data;
BYTE far * wptr;
outp(0x8102,(inp(0x8102)|2)); /* set VME E-page enable bit */
outp(0x8150,(WORD)(addr >> 24)); /* A31–A24 */
outp(0x8151,2 | (((addr << 8) >> 30) << 6));
/* A23–A22 and address modifier for A32 supervisory data access */
outp(0x8130,(WORD)((addr << 10) >> 24); /* A21–A16 */
wptr = (BYTE far *) (0xE00 (addr & 0X0000FFFFL));
*wptr = data; /* Write through window */
The success of the access can be checked either by enabling BERR as an interrupt or by
looking at the BERR bit in the event state register (8154h) after each access.
Low-Level Handling of VMEbus Interrupts
The following is a description of how VMEbus interrupts (IRQ1–IRQ7), VXIbus message
interrupts and error interrupts (BERR, ACFAIL, WDT, and so on.) should be handled on
the EPC-8A. Note that, in general, the use of EPConnect is highly recommended for
handling interrupts.
• Enable the appropriate registers (VME Interrupt enable (8153h) and VME Event
enable (8155h) registers) to allow the interrupts you want to respond to.
• Enable IRQ10 on the EPC’s equivalent of the 8259 interrupt controller.
• A VXIbus message interrupt is generated when a master (this EPC-8A or another
master) writes to the Message Low register (16-bit) from the VMEbus. A message
interrupt does not occur when the EPC-8A writes to its own message register(s) from
the PC I/O space.
• Keep in mind that while PC/AT interrupts are edge sensitive, VMEbus interrupts are
level sensitive. As such, you must ensure that:
1. The 8259 interrupt controller is enabled to capture interrupts before a VMEbus
interrupt occurs (otherwise VMEbus interrupts are totally missed) and
2. You must handle all pending VMEbus interrupts before returning from the
interrupt handler.
• When an interrupt occurs, first acknowledge the interrupt to the PC/AT 8259 interrupt
controllers by sending both interrupt controllers an End-of-Interrupt (EOI).
• You must make sure that your interrupt handler code is not re-entered while
dispatching interrupts. Either all interrupts should be disabled or IRQ10 should be
VMEbus Address bits 21–16 Res Res