Smart Module Series
SC606T Series Hardware Design
SC606T_Series_Hardware_Design 47 / 116
application is equipped with a 3.3 V UART interface. The level translator chip TXS0104EPWR provided
by Texas Instruments is recommended. The following figure shows a reference design for the level
translator chip.
VCCA
VCCB
OE
A1
A2
A3
A4
GND
B1
B2
B3
B4
LDO5_1P8
UART 5_ RTS
UART5_ RXD
UART 5_ CTS
UART5_ TXD
RXD_3.3V
CTS_3.3V
TXD_3.3V
VDD_3.3V
TXS0104 EPWR
C1
100 pF
C2
U1
100 pF
RTS_3.3V
Figure 13: Reference Design for Level Translator Chip (for UART5)
The following figure is an example connection between the module and PC. A voltage level translator and
an RS-232 transceiver are recommended to be added between the module and PC, as shown in the
figure below:
TXS0104 EPWR
RXD_3.3V
CTS_3.3V
VCCA
Module
GND
GND
1.8V
VCCB
3.3V
DIN 1
ROUT 3
ROUT 2
ROUT 1
DIN 4
DIN 3
DIN 2
DIN 5
FORCEON
3.3V
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
RIN3
RIN2
RIN1
VCC
GND
OE
SN65C3238
DB-9
RTS
TXD
CTS
RXD
GND
RTS_3.3V
UART5_TXD
UART5_RTS
UART5_RXD
UART5_CTS
TXD_1.8V
RTS_1.8V
RXD_1.8V
CTS_1.8V
/FORCEOFF
/INVALID
R1OUTB
TXD_3.3V
Figure 14: RS-232 Level Match Circuit (for UART5)
The level translation reference designs for UART2 and UART4 are similar with those for UART5.
NOTE