Smart Module Series
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In 3-camera applications, CSI1_LN3_P and CSI1_LN3_N are used as CLK_P and CLK_N of camera1,
CSI1_LN2_P and CSI1_LN2_N are used as the LN_P and LN_N of camera1.
3.20.1. Design Considerations
⚫
Special attention should be paid to the pin definition of LCM/camera connectors. Make sure the
module and the connectors are correctly connected.
⚫
MIPI are high speed signal lines, supporting maximum data rate of up to 2.1 Gbps. The differential
impedance should be controlled to 100 Ω. Additionally, it is recommended to route the trace on the
inner layer of PCB, and do not cross it with other traces. For the same group of DSI or CSI signals,
keep all the MIPI traces of the same length. In order to avoid crosstalk, keep a distance of 1.5 times
the trace width among MIPI signal lines. During impedance matching, do not connect GND on
different planes to ensure impedance consistency.
⚫
It is recommended to select a low-capacitance TVS for ESD protection and the recommended
parasitic capacitance should be below 1 pF.
⚫
Route MIPI traces according to the following rules:
a) The total trace length should not exceed 305 mm;
b) Control the differential impedance
to 100 Ω ±10 %;
c) Control intra-lane length difference within 0.67 mm;
d) Control inter-lane length difference within 1.3 mm.
Table 26: MIPI Trace Length Inside the Module
Pin Name
Pin No.
Length (mm)
Length Difference (P - N)
52
DSI_CLK_N
12.40
0.00
53
DSI_CLK_P
12.40
54
DSI_LN0_N
11.75
-0.10
55
DSI_LN0_P
11.65
56
DSI_LN1_N
9.40
-0.10
57
DSI_LN1_P
9.30
58
DSI_LN2_N
9.60
0.00
59
DSI_LN2_P
9.60
60
DSI_LN3_N
12.35
0.00
NOTE
