Quectel RM510Q-GL, Проектирование аппаратного обеспечения

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5G Module Series
RM510Q-GL Hardware Design
RM510Q-GL_Hardware_Design 23 / 88
49 PCIE_RX_P AI PCIe receive (+)
50 PCIE_RST_N DI, OD
PCIe reset.
Active LOW
51 GND Ground
52 PCIE_CLKREQ_N DO, OD
PCIe clock request.
Active LOW
53 PCIE_REFCLK_M AI, AO PCIe reference clock (-)
54 PCIE_WAKE_N DO, OD
PCIe wake up
Active LOW
55 PCIE_REFCLK_P AI, AO
PCIe reference clock
(+)
56 RFFE_CLK*
1)
DO, PD
Used for external MIPI
IC control
1.8 V
57 GND Ground
58 RFFE_DATA*
1)
DO, PD
Used for external MIPI
IC control
1.8 V
59 LAA_TX_EN* DO
Notification from
transceiver to WLAN
when LTE transmitting
1.8 V
60 WLAN_TX_EN* DI
Notification from WLAN
to SDR while
transmitting
1.8 V
61 ANTCTL1* DO, PD Antenna GPIO control 1.8 V
62 COEX_RXD* DI, PD
LTE/WLAN coexistence
receive data
1.8 V
63 ANTCTL2* DO, PD Antenna GPIO control 1.8 V
64 COEX_TXD* DO, PD
LTE/WLAN coexistence
transmit data
1.8 V
65 RFFE_VIO_1V8
1)
PO
Power supply for
antenna tuner
1.8 V
66 USIM1_DET
DI
;
PD
(U)SIM1 card hot-plug
detect
1.8 V
67 RESET# DI, PU
Reset the module.
Active LOW.
V
IH
max = 1.575 V
V
IH
min = 1.25 V
V
IL
max = 0.45 V
Internally pulled
up to 1.5 V with a
100 kΩ resistor
68 AP2SDX_STATUS DI, PD
Status indication from
AP
1.8 V
69 CONFIG_1 DO Connected to GND