5G Module Series
RM505Q-AE Hardware Design
RM505Q-AE_Hardware_Design 29 / 79
Host
Module
RESET_N
Reset
Logic
GPIO
67
VDD 1.5 V
Reset pulse
200-700 ms
R1
100K
R5
100K
R4
10R
Q2
NMOS
Figure 11: Reference Circuit for RESET_N with NMOS Driving Circuit
Module
RESET_N
Reset
Logic
67
VDD 1.5 V
200-700 ms
S1
TVS
R1
100K
33 pF
C1
Note:
The capacitor C1 is recommended to be less than 47 pF.
Figure 12: Reference Circuit for RESET_N with Button
The timing of reset scenario is illustrated in the following figure.