Quectel RM502Q-GL, Проектирование аппаратного обеспечения

Страница: 21 / 86

5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 20 / 77
51 GND GND Ground
52 CLKREQ# PCIE_CLKREQ_N DO
PCIe clock request.
Active LOW.
Open drain
53 REFCLKn PCIE_REFCLK_M
AI,
AO
PCIe reference clock (-)
54 PEWAKE# PCIE_WAKE_N DO
PCIe PME wake.
Active LOW.
Open drain
55 REFCLKp PCIE_REFCLK_P
AI,
AO
PCIe reference clock (+)
56 NC RFFE1_CLK DO RFFE1 serial interface clock
1.8 V power
domain
57 GND GND Ground
58 NC RFFE1_DATA DO RFFE1 serial interface data
1.8 V power
domain
59
ANTCTL0
(O)(0/1.8 V)
LAA_TX_EN DO
Notification from SDR to WL
when LTE transmitting
1.8 V power
domain
60 COEX3 WLAN_TX_EN DI
Notification from WL to SDR
while transmitting
1.8 V power
domain
61
ANTCTL1
(O)(0/1.8 V)
RFFE0_DATA DO RFFE0 serial interface data
1.8 V power
domain
62 COEX2 COEX_RXD DI
LTE/WLAN coexistence
receive data
1.8 V power
domain
63
ANTCTL2
(O)(0/1.8 V)
RFFE0_CLK DO RFFE0 serial interface clock
1.8 V power
domain
64 COEX1 COEX_TXD DO
LTE/WLAN coexistence
transmit data
1.8 V power
domain
65
ANTCTL3
(O)(0/1.8 V)
RFFE_VIO_1V8 PO Power supply for RFFE
1.8 V power
output
66 SIM_DETECT USIM1_DET DI
(U)SIM1 card insertion
detection
Internally pulled
up to 1.8 V
67
RESET#
(I)(0/1.8 V)
RESET_N DI
Reset the module.
Active LOW.
Internally pulled
up to 1.8 V with
a 100k
Ω
resistor
68
SUSCLK(32
kHz)
AP2SDX_STATUS DI Status indication from AP
1.8 V power
domain
69 CONFIG_1 CONFIG_1 DO Connected to GND internally
70 3.3 V VCC PI Power supply
V
min
= 3.135 V
V
norm
= 3.7 V
V
max
= 4.4 V