
5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 34 / 77
AC coupling capacitors C5 and C6 must be placed close to the host and close to each other. C1 and C2
have been integrated inside the module, so do not place these two c
apacitors on customers’ schematic
and PCB. In order to ensure the signal integrity of USB 2.0 data traces, R1, R2, R3 and R4 must be
placed close to the module, and the stubs must be minimized in PCB layout.
In order to ensure that the USB interface designs corresponds with USB specifications, please comply
with the following principles:
⚫
Do not route USB traces under or close to crystals, oscillators, magnetic components, RF signal
traces or other high noisy signal traces. It is important to route USB differential pairs in inner layer of
the PCB, and surround the traces with ground on that layer and with ground planes above and below.
⚫
The impedance of USB 3.1 & 2.0 differential trace is 90
Ω.
⚫
For USB 2.0 signal traces, the trace length must be less than 120 mm, the differential data pair
matching is less than 2 mm (15 ps).
⚫
If USB connector is used, please keep the ESD protection components as close as possible to the
USB connector. Pay attention to the influence of junction capacitance of ESD protection components
on USB 2.0 data traces. The capacitance value of ESD protection components should be less than
2.0 pF for USB 2.0.
⚫
If possible, reserve four 0
Ω resistors (R1–R4) on USB_DP and USB_DM as shown in
the above
figure.