5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 19 / 77
28
GPIO_8
/AUDIO_3
PCM_SYNC
IO
PCM data frame sync
1.8 V power
domain
29
PETn1
USB_SS_TX_M
AO
USB 3.1 transmit data (-)
30
UIM_RESET(O)
USIM1_RST
DO
(U)SIM1 card reset
1.8/3.0 V power
domain
31
PETp1
USB_SS_TX_P
AO
USB 3.1 transmit data (+)
32
UIM_CLK(O)
USIM1_CLK
DO
(U)SIM1 card clock
1.8/3.0 V power
domain
33
GND
GND
Ground
34
UIM_DATA(I/O)
USIM1_DATA
IO
(U)SIM1 card data
1.8/3.0 V power
domain
35
PERn1
USB_SS_RX_M
AI
USB 3.1 receive data (-)
36
UIM_PWR(O)
USIM1_VDD
PO
Power supply for (U)SIM1
card
1.8/3.0 V power
domain
37
PERp1
USB_SS_RX_P
AI
USB 3.1 receive data (+)
38
NC
SDX2AP_STATUS
DO
Status indication to AP
1.8 V power
domain
39
GND
GND
Ground
40
GPIO_0
/SIM_DET2
USIM2_DET
DI
(U)SIM2 card insertion
detection
Internally pulled
up to 1.8 V
41
PETn0
PCIE_TX_M
AO
PCIe transmit data (-)
42
GPIO_1
/SIM_DAT2
USIM2_DATA
IO
(U)SIM2 card data
1.8/3.0 V power
domain
43
PETp0
PCIE_TX_P
AO
PCIe transmit data (+)
44
GPIO_2
/SIM_CLK2
USIM2_CLK
DO
(U)SIM2 card clock
1.8/3.0 V power
domain
45
GND
GND
Ground
46
GPIO_3
/SIM_RST2
USIM2_RST
DO
(U)SIM2 card reset
1.8/3.0 V power
domain
47
PERn0
PCIE_RX_M
AI
PCIe receive data (-)
48
GPIO_4
(SIM_PWR2)
USIM2_VDD
PO
Power supply for (U)SIM2
card
1.8/3.0 V power
domain
49
PERp0
PCIE_RX_P
AI
PCIe receive data (+)
50
PERST#
PCIE_RST_N
DI
PCIe reset.
Active LOW.
Open drain