Automotive Module Series
AG525R-GL QuecOpen
Hardware Design
AG525R-GL_QuecOpen_Hardware_Design 61 / 104
Table 21: Parameters of SPI Interface Timing
The module provides a 1.8 V SPI interface. A level translator should be used between the module and the
host if customers’ application is equipped with a 3.3 V processor or device interface.
3.15. RGMII Interface
The module includes an integrated Ethernet MAC with an RGMII interface. Key features of the RGMII
interface are shown below:
Support IEEE 1588-2008, IEEE 802.1AS-2011 and 802.1-Qav-2009
Half/full duplex for 10/100/1000 Mbps
Support VLAN tagging
Can be used to connect to external Ethernet PHY like 88EA1512, or an external switch
Table 22: Pin Definition of RGMII Interface
Parameter
Description
Min.
Typ.
Max.
Unit
T SPI
clock
period
20.0
-
- ns
t(ch)
SPI clock high-level time
9.0
-
-
ns
t(cl)
SPI clock low-level time
9.0
-
-
ns
t(mov)
SPI master data output valid time
-5.0
-
5.0
ns
t(mis)
SPI master data input setup time
5.0
-
-
ns
t(mih)
SPI master data input hold time
1.0
-
-
ns
Pin Name
Pin No. I/O
Description
Comment
RGMII_MD_IO
10
IO
RGMII MDIO management data
Power domain determined
by RGMII_PWR_IN
RGMII_MD_CLK
11
DO
RGMII MDC management clock
RGMII_RX_0
13
DI
RGMII receive data bit 0
RGMII_RX_1
14
DI
RGMII receive data bit 1
NOTE