Automotive Module Series
AG525R-GL QuecOpen
Hardware Design
AG525R-GL_QuecOpen_Hardware_Design 29 / 104
I2C1_SDA
80
OD I2C1 serial data
resistor is required.
1.8 V only.
Can be configured
to GPIO.
If unused, keep
them open.
I2S Interface (for Codec Configuration by Default)
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
CDC_RST 77
DO
Codec
reset
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
Can be configured
to GPIO.
If unused, keep
them open.
I2S_MCLK 81
DO
Clock output for
codec
V
OL
max = 0.45 V
V
OH
min = 1.35 V
I2S_WS
73
IO
I2S word select
V
OL
max = 0.45 V
V
OH
min = 1.35 V
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
I2S_SCK 75
DO
I2S
clock
V
OL
max = 0.45 V
V
OH
min = 1.35 V
I2S_DIN
76
DI
I2S data in
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
I2S_DOUT
78
DO I2S data out
V
OL
max = 0.45 V
V
OH
min = 1.35 V
PCM Interface
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
PCM_SYNC 265
IO
PCM data frame
sync
V
OL
max = 0.45 V
V
OH
min = 1.35 V
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
Can be configured
to GPIO.
If unused, keep
them open.
PCM_CLK 262
IO
PCM
clock
V
OL
max = 0.45 V
V
OH
min = 1.35 V
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V