Automotive Module Series
AG525R-GL QuecOpen
Hardware Design
AG525R-GL_QuecOpen_Hardware_Design 67 / 104
The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2
specifications.
It is important to route the PCIe signal traces as differential pairs with ground surrounded. And the
differential impedance is 95
Ω
±10%.
For PCIe signal traces, the maximum length of each differential data pair (TX/RX/REFCLK) is
recommended to be less than 270 mm, and each differential data pair matching should be less than
0.7 mm (5 ps).
Spacing data lane-to-lane (intra-interface) is three times of line width.
Spacing to all other signals (inter-interface) is four times of line width.
Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is
important to route the PCIe differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
3.17. ADC Interfaces
The module provides three analog-to-digital converter (ADC) interfaces. The voltage value on ADC pins
can be read via
AT+QADC=<port>
command, through specifying
<port>
as 0, 1 or 2. For more details
about the AT command, see
document [3]
.
AT+QADC=0
: read the voltage value on ADC0
AT+QADC=1
: read the voltage value on ADC1
AT+QADC=2
: read the voltage value on ADC2
In order to improve the accuracy of ADC, the traces of ADC interfaces should be surrounded by ground.
Table 24: Pin Definition of ADC Interfaces
Pin Name
Pin No.
Description
ADC1
245
General purpose ADC interface
ADC0
247
General purpose ADC interface
ADC2
139
General purpose ADC interface
Table 25: Characteristic of ADC Interface
Parameter
Min.
Typ.
Max.
Unit