LTE-A Module Series
EG18 Hardware Design
EG18_Hardware_Design 65 / 104
matching should be less than 2mm (15ps).
For PCIe signal traces, the maximum length of each differential data pair (TX/RX) is recommended to
be less than 250mm, and each differential data pair matching should be less than 0.7mm (5ps).
Do not route signal traces under crystals, oscillators, magnetic devices or RF signal traces. It is
important to route the PCIe differential traces in inner-layer of the PCB, and surround the traces with
ground on that layer and with ground planes above and below.
If possible, reserve a 0
Ω resistor on USB_DP and USB_DM lines, respectively.
USB is required because PCIe does not support features such as firmware upgrade, GNSS NMEA output
and software debugging. Firmware upgrade must be realized over USB 2.0, while GNSS NMEA output
and software debugging can be realized over USB 2.0/3.0 (USB 2.0 is recommended).
3.18. SDIO Interface*
EG18 provides one SDIO interface which supports SD 3.0 protocol and eMMC*. The following table
shows the pin definition.
Table 26: Pin Definition of SDIO Interface
Pin Name
Pin No.
I/O
Description
Comment
SD_VDD
46
PO
SD card application
: SDIO pull up
power source
eMMC application
: Keep it open
when used for eMMC
1.8V/3.0V configurable
output.
Cannot be used for SD
card power supply.
SD_DATA3
48
IO
SDIO data signal (bit 3)
If unused, keep it open.
SD_DATA2
47
IO
SDIO data signal (bit 2)
If unused, keep it open.
SD_DATA1
50
IO
SDIO data signal (bit 1)
If unused, keep it open.
SD_DATA0
49
IO
SDIO data signal (bit 0)
If unused, keep it open.
SD_CMD
51
IO
SDIO command signal
If unused, keep it open.
SD_DET
52
DI
SD card insertion detection
1.8V power domain.
If unused, keep it open.
SD_CLK
53
DO
SDIO clock signal
If unused, keep it open.
NOTE