LTE-A Module Series
EG18 Hardware Design
EG18_Hardware_Design 51 / 104
3.10.2. Debug UART Interface
The following table shows the pin definition of debug UART interface.
Table 13: Pin Definition of Debug UART Interface
3.10.3. BT UART Interface
The following table shows the pin definition of BT UART interface.
Table 14: Pin Definition of the BT UART Interface
3.10.4. UART Application
EG18 provides 1.8V UART interfaces. A level translator should be used if the application is equipped with
a 3.3V UART interface.
The logic levels are described in the following table.
Table 15: Logic Levels of Digital I/O
Pin Name
Pin No.
I/O
Description
Comment
DBG_RXD
136
DI
Receive data
1.8V power domain
DBG_TXD
137
DO
Transmit data
1.8V power domain
Pin Name
Pin No.
I/O
Description
Comment
BT_EN
3
DO
BT function enable control
1.8V power domain
If unused, keep it open.
BT_TXD
163
DO
Transmit data
BT_CTS
164
DO
Clear to send
BT_RXD
165
DI
Receive data
BT_RTS
166
DI
Request to send
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.6
V
