LTE-A Module Series
EG06 Hardware Design
EG06_Hardware_Design 59 / 89
3.20. SPI Interface
EG06 provides one SPI interface which only supports master mode with a maximum clock frequency up
to 50MHz. The following table shows the pin definition of SPI interface.
Table 25: Pin Definition of the SPI Interface
The following figure shows the timing relationship of SPI interface. The related parameters of SPI timing is
shown as the following table.
SPI_CS_N
SPI_CLK
SPI_MOSI
MSB
1
2
SPI_MISO
3
T
t(mov)
4
t(mis)
t(mih)
t(ch) t(cl)
Figure 29: SPI Interface Timing
Pin Name
Pin No.
I/O
Description
Comment
SPI_CS
79
DO
Chip select of SPI interface
1.8V power domain.
If unused, keep them open.
SPI_MOSI
77
DO
Master output slave input of SPI
interface
SPI_MISO
78
DI
Master input slave output of SPI
interface
SPI_CLK
80
DO
Clock signal of SPI interface
