Quectel EG06 Series, Руководство пользователя

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LTE-A Module Series
EG06 Hardware Design
EG06_Hardware_Design 19 / 89
3.2. Pin Assignment
The following figure shows the pin assignment of EG06 module.
2
9
9
176
2
9
8
174
172
170
168
166
164
162
160
158
156
154
152
150
148
146
144
142
140
138
136
134
132
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175
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169
167
165
163
161
159
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155
153
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149
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145
143
141
139
137
135
133
131
1
2
9
1
2
7
1
2
5
1
2
3
1
2
1
1
1
9
1
1
7
1
1
5
1
1
1
1
0
9
1
0
7
1
0
5
1
0
3
1
0
1
9
9
9
7
9
5
1
2
8
1
1
3
1
2
6
1
2
4
1
2
2
1
2
0
1
1
8
1
1
6
1
1
4
1
1
2
1
1
0
1
0
8
1
0
6
1
0
4
1
0
2
1
0
0
9
8
9
6
2
1
4
2
1
3
2
1
2
2
1
1
2
1
0
2
0
9
2
0
8
2
0
7
2
0
6
2
0
5
2
0
4
2
0
3
2
0
2
2
0
1
2
0
0
1
9
9
1
9
8
9
3
9
1
8
9
9
4
9
2
9
0
1
9
7
1
9
6
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
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75
77
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81
83
85
87
42
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60
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64
66
68
70
72
74
76
78
80
82
84
86
88
4
1
3
9
3
7
3
5
3
3
3
1
2
9
2
7
2
3
2
1
1
9
1
7
1
5
1
3
1
1
9 7
4
0
2
5
3
8
3
6
3
4
3
2
3
0
2
8
2
6
2
4
2
2
2
0
1
8
1
6
1
4
1
2
1
0
8
1
9
5
1
9
4
1
9
3
1
9
2
1
9
1
1
9
0
1
8
9
1
8
8
1
8
7
1
8
6
1
8
5
1
8
4
1
8
3
1
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2
1
8
1
1
8
0
1
7
9
5 3 1
6 4 2
1
7
8
1
7
7
Power Pins GND Pins GPIO and Other Pins RESVRVED Pins
2
9
7
296
216 217 218 215 219 220 221 222 223
224
233
242
251
260
269
278
287
225
234
243
252
261
270
279
288
226
235
244
253
262
271
280
289
227
236
272
281
290
228
237
273
282
291
229
238
274
283
292
230
239
248
257
266
275
284
293
231
240
249
258
267
276
285
294
232
241
250
259
268
277
286
295
PCIe Pins PCM Pins USIM Pins USB Pins
IIC Pins
SD Pins
ADC Pins UART Pins
SPI Pins
ANT Pins CLK Pins
R
E
S
E
T
_
N
P
W
R
K
E
Y
B
T
_
E
N
P
M
_
E
N
A
B
L
E
U
S
IM
_
P
R
E
S
E
N
C
E
U
S
IM
_
C
L
K
U
S
IM
_
D
A
T
A
U
S
IM
_
V
D
D
U
S
IM
_
R
S
T
U
S
B
_
V
B
U
S
U
S
B
_
D
M
U
S
B
_
D
P
U
S
B
_
ID
U
S
B
_
S
S
_
T
X
_
M
U
S
B
_
S
S
_
T
X
_
P
U
S
B
_
S
S
_
R
X
_
P
U
S
B
_
S
S
_
R
X
_
M
I2C_SDA
I2C_SCL
SD_VDD
SD_DATA2
SD_DATA3
SD_DATA0
SD_DATA1
SD_CMD
SD_DETECT
SD_CLK
CTS
RTS
RXD
DCD
TXD
RI
DTR
PCM_SYNC
PCM_CLK
PCM_IN
PCM_OUT
SPI_MOSI
SPI_CS
SPI_MISO
SPI_CLK
VBAT_RF
VBAT_RF
VBAT_RF
VBAT_RF
A
N
T
_
M
A
IN
A
N
T
_
G
N
S
S
A
N
T
_
D
IV
RESERVED
DBG_RXD
GPIO1
USB_BOOT
VDD_P2
DBG_TXD
GPIO2
OTG_PWR_EN
COEX_UART_TX
NET_MODE
WLAN_EN
W_DISABLE#
SLEEP_IND
COEX_UART_RX
WAKEUP_IN
RESERVED
VBAT_BB
VBAT_BB
WAKE_ON_WIRELESS
BT_TXD
BT_RXD
BT_CTS
BT_RTS
VDD_EXT
WLAN_SLP_CLK
GND
NET_STATUS
STATUS
ADC0
ADC1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P
C
IE
_
R
E
F
C
L
K
_
P
P
C
IE
_
R
E
F
C
L
K
_
M
P
C
IE
_
T
X
_
M
P
C
IE
_
T
X
_
P
P
C
IE
_
R
X
_
M
P
C
IE
_
R
X
_
P
P
C
IE
_
C
L
K
_
R
E
Q
_
N
P
C
IE
_
R
S
T
_
N
P
C
IE
_
W
A
K
E
_
N
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U
S
IM
_
G
N
D
245 246 247
254 255 256
263 264 265
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
G
N
D
R
E
S
E
R
V
E
D
G
N
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
G
N
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
G
N
D
G
N
D
G
N
D
G
N
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
G
N
D
R
E
S
E
R
V
E
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
R
E
S
E
R
V
E
D
RESERVED
RESERVED
RESERVED
RESERVED
Figure 2: Pin Assignment (Top View)