QUANTA W Mainboard Series S210-MBT2W, Техническое руководство

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A
BOUT THE
S
ERVER
S210-MBT2W F
EATURES
1-2
[1.1.14] CPU PCI
Express Configura-
tion
[1.1.15] Integrated I/O Configuration:

PCI Express Gen3: 40 lanes

PCIe Master controllers: 10 Full peer-to-peer
support between PCI-Express interfaces

PCI-Express Base Specification: Revision 2 and
3 compliant

IOAT4 Support: PCIe Gen3 caching hints I/O
Virtualization: VT-d 2 Supported

Crystal Beach Supported

PCIe Master Controller configuration:

IOU 0: 4 Master Controllers

IOU 1: 4 Master Controllers

IOU 2: 2 Master Controllers

Supported configurations:

IOU 2 Port 0: 1 x4 ESI/DMI port in Gen2
mode

Independent logic operation from x8. Can be
strapped to operate in PCIe-mode

IOU 2 Port 1: 2 x4, or 1x8 (IOU to connect to
Patsburg)

IOU 0 Port 2: 4 x4, or 1 x8 and 2 x4, or 2 x8,
or 1 x16

IOU 1 Port 3: 4 x4, or 1 x8 and 2 x4, or 2x8,
or 1 x16
[1.1.6] S210-MBT2W Feature Set (Continued)
[1.1.7] F
EATURE
[1.1.8] D
ESCRIPTION
[1.1.16] CPU PCI
Express Configura-
tion

IOU to Port Mapping

Port 0 x4 = IOU2 = xxESI_xx_ [3:0]

Port 1 x8 = IOU2 = xxPE2_xx_ [7:0]

Port 2 x16 = IOU0 = xxPE0_xx_ [15:0]

Port 3 x16 = IOU1 = xxPE1_xx_ [15:0]
[1.1.17] Server
South Bridge
[1.1.18] Patsburg SSB:

Patsburg –A: TDP 8.0W

Patsburg –A with 8 Drive Upgrade Options: TDP
11.50W
[1.1.19] I/O Architecture: Upstream Interfaces:

DMI/ESI x4 Gen2 interface

PCI-E x4 Gen3 interface:

Connect to SNB-EP / IVB-EP IOU2 Port 0:
x4 link: SNB-EP / IVB-EP Interface:
xxPE2_xx_[3:0]

Downstream Interfaces:

PCI Express Gen2: 8 Lanes

PCIe Master Controllers: 8

Supported Configurations: 8 x1, or 4 x2, or 2
x4

Non-Supported Configuration: 1 x8
[1.1.6] S210-MBT2W Feature Set (Continued)
[1.1.7] F
EATURE
[1.1.8] D
ESCRIPTION