QUANTA W Mainboard Series S210-MBT2W, Техническое руководство

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A
BOUT THE
S
ERVER
THERMTRIP#
1-78
[1.3.212] THERMTRIP#
[1.3.213] THERMTRIP# pin behaviour on the Romley platform
can be configured as follows:

SNB-EP / IVB -EP Memory Subsystem (DIMMs) Cata-
strophic Thermal Event.

SNB –EP / IVB -EP Processor Catastrophic Thermal
Event. (DEFAULT)

Both SNB-EP / IVB-EP Processor and Memory Subsys-
tem (DIMM) Catastrophic Thermal Event.

None
[1.3.214] On the S210-MBT2W baseboards the THERMTRIP#
pin will be configured to signal only Processor catastrophic ther-
mal events. To detect Memory DIMM catastrophic thermal
events on the baseboard the ASPEED AST2300 BMC will mon-
itor the Memory DIMM EVENT# signals. This will require the
BIOS MRC code to pre-set the DIMM TSOD EVENT_N signal
to trigger upon crossing a preconfigured range.
[1.3.216] The THERMTRIP_N signal is tied to a unique GPI on
the ASPEED AST2300 BMC for Firmware to monitor these
events. THERMTRIP# will also be tied to the Patsburg SSB
THRMTRIP_N input to cause an automatic Power Off condition
when it is activated as required by the Sandy Bridge –EP / Ivy
Bridge -EP EMTS document. A high-level architecture diagram
is attached below for reference.
[1.3.217] THERMTRIP# Connectivity
Note:
[1.3.215] Memory TSOD EVENT# signals will be connected
to directly to the ASPEED AST2300 for proper error detection
and FRU isolation. At the same time the Memory TSOD
EVENT# signals must be combined and combined with the
Processor THERMTRIP# signals before it is taken to the
Patsburg SSB THERMTRIP_N input signal through a
required delayed circuit.
Note:
[1.3.218] The IVB-EP Processor Thermtrip# signal must be
voltage translated from a Vhigh(min) of 0.95V. The voltage
translation circuit designed by APD must cover both SNB-EP
and IVB-EP processors.