If no serial EEPROM is present:
3.11.1 Booting the PCI 9054RDK-Lite
with No EEPROM or a Blank
EEPROM
Change the RDK board’s factory installed
pull-up resistor on the PCI 9054 EEDI/EEDO
input to a pull-down resistor, as follows:
The PCI 9054 default register value for the
Expansion ROM Range register requests
64K of Expansion ROM space. Unless a
programmed EEPROM initializes this
register with the value 0, BIOS will perform a
read from Local bus address 0 (the default
Expansion ROM Base Address register
(EROMBA) value) to determine whether a
valid ROM image exists. The default value
for register bit LBRD0[22] enables the
READY# input for Expansion ROM space,
requiring that the READY# input be asserted
to complete the data phase of that read.
The Local bus access also requires
successful arbitration and active clock
(LCLK).
Remove the 10K resistor R74 and install a
1K resistor at R19.
Note.
If a programmed EEPROM is later
added to the modified RDK, the pull-down
must be changed back to a pull-up. Remove
the 1K resistor at R19 and install a 10K
resistor at R74.
To modify the RDK to pull the READY#
input low:
a. Lift from the board the Altera CPLD
D15/READY# pin (84).
b. Tie the PCI 9054 READY# pin (135) low
through a 10K pull-down to ground. The
READY# signal is accessible at the
following locations: PCI 9054 pin 135,
the solder pad to CPLD pin 84, test
header LAH6 pin 12, POM connector
pin 75, and either side of R71.
Note that a spare 10K resistor is
available at RN4[4:5]. Since pin 6 of
RN4 is already grounded, pin 5 can be
soldered to pin 6 to ground one leg of
the resistor. A wire can then be soldered
to connect R71 to RN4-4.
PCI 9054RDK- LITE Hardware Reference Manual v1.3
14
© 2006 PLX Technology, Inc. All rights reserved.
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