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PCI 9054RDK- LITE Hardware Reference Manual v1.3

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© 2006 PLX Technology, Inc. All rights reserved.

3.7 PLX Option Module Connector

The PLX Option Module Connector resides
directly on the 32-bit multiplexed J mode
Processor/Local Bus. Either/both a master
and/or slave device may be connected to this
connector, which resides at address range 4000
0000 - 4FFF FFFF. The external arbiter in the
CPLD uses CS0# to select the POM module.
Page 5 of the RDK schematic details all of the
signals of the 100-pin connector. If desired, this
connector can be used for expansion and
prototyping.

3.8 Hardware

Modules

The RDK-LITE provides four hardware modules:
1) RS232 interface, 2) debug and status LEDs,
3) reset circuitry, and 4) flash ROM socket. This
is in addition to the clock generator used to
provide the 50 MHz Processor/Local Bus clock
to the PCI 9054, CPLD, POM, and the
Synchronous SRAM.

3.8.1 RS232

Interface

The RS232 interface circuit combines a DB9
male connector with an RS232 transceiver. The
transceiver chip is made by Maxim Integrated
Products and can be hardware configured or
software programmed as Data Terminal
Equipment (DTE) or Data Circuit Equipment
(DCE).

3.8.2

Debug and Status LEDs

There are four green user-defined LEDs near
the top edge of the RDK board. The anode of
each LED is

connected to

3.3V

DC

through a

150-ohm ¼ watt resistor. The cathode of each
LED is connected to a prototyping pad for
customer use. As long as an active low signal
can sink 16 – 20 mA of current, it can directly
drive the LEDs without changing the resistor
value.

3.8.3 Reset

Circuitry

3.8.3.1 Power-on-Reset

Power-on-reset is controlled by an
external 3.3-Volt power supply
supervisor. The valid power-on-reset
period is 1ms, which is hardwired into
the supply supervisor IC.

3.8.3.2

Reset Pushbutton Switch

The Reset Pushbutton switch allows the
user to reset the Processor/Local Bus
side of the board only. When this
pushbutton switch is pressed, a manual
reset can be generated to reset the
devices on the PCI 9054
Processor/Local Bus.

3.8.4

Flash ROM Socket

A 32-pin PLCC footprint and related PLCC
socket are provided on the RDK. It can be used
to install a 3.3 volt 512KB byte-wide flash
memory device. It can be used to store the
firmware for booting Processor/Local Bus
master devices such as microprocessors or
DSPs. The flash ROM footprint is pre-connected
to power and ground. The prototyping pads are
provided for all control signal pins as well as all
address and data lines.

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Содержание PCI 9054RDK-LITE

Страница 1: ...PCI 9054RDK LITE Hardware Reference Manual ...

Страница 2: ......

Страница 3: ...PCI 9054RDK LITE Hardware Reference Manual Version 1 3 January 2006 http www plxtech com Website http www plxtech com support Technical Support 408 774 9060 Phone 800 759 3735 408 774 2169 Fax ...

Страница 4: ... to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX products PLX Technology and the PLX logo are registered trademarks of PLX Technology Inc Other brands and names are the property of their respective owners Order Number CPCI 9054 LITE RDK HRM P1 1 3 Printed in the USA January 2006 ...

Страница 5: ...claims by third parties which may arise through the use of the Rapid Development Kit RDK or for any damage or loss caused by deletion of data as a result of malfunction or repair ABOUT THIS MANUAL This document describes the PLX PCI 9054RDK LITE Rapid Development Kit from a hardware perspective It contains a description of all major functional circuit blocks on the board This manual also includes ...

Страница 6: ......

Страница 7: ...OM Contents 6 3 4 Synchronous SRAM 9 3 5 Altera CPLD 9 3 6 Test Headers 9 3 7 PLX Option Module Connector 10 3 8 Hardware Modules 10 3 8 1 RS232 Interface 10 3 8 2 Debug and Status LEDs 10 3 8 3 Reset Circuitry 10 3 8 3 1 Power on Reset 10 3 8 3 2 Reset Pushbutton Switch 10 3 8 4 Flash ROM Socket 10 3 9 Prototyping Area 11 3 9 1 Thirty 30 Surface Mount Footprints 11 3 9 2 Three Common BGA Landscap...

Страница 8: ...3 1 PCI 9054RDK LITE Hardware Block Diagram 4 Figure 3 2 BGA Landscapes 12 LIST OF TABLES 5 Table 3 1 PCI 9054RDK LITE Memory Map 7 Table 3 2 Long Serial EEPROM Load Registers 8 Table 3 3 Extra Long Serial EEPROM Load Registers 11 Table 3 4 Thirty 30 Surface Mount Footprints 13 Table 3 5 PCI 9054 Mode Setting 23 Table 5 1 Bill of Materials PCI 9054RDK LITE Hardware Reference Manual v1 3 viii 2006 ...

Страница 9: ...ader JPOM connector DB9 LEDs EEPROM OSC reset cct CPLD header flash ROM socket 5Volt rail 3 3volt rail 3 3volt rail groundrail groundrail 20x20x1 5mm BGA1 landscape 26x26x0 05 BGA2 landscape 25x25x1mm BGA3 landscape PLCC footprints QFP footprint 54 pin TSOP 54 pin TSOP QFP QFP QFPfootprints footprints footprints QFP footprint USB connector RJ45 connector 48 pin SSOP 48 pin SSOP 28 pin SOIC 28 pin ...

Страница 10: ...tatus debug LEDs In system programmable CPLD with equations in Verilog provide chip selects Processor Local Bus arbiter and SRAM control Built in DB9 connector and programmable DTE DCE RS232 transceiver for easy addition of a serial port A pushbutton switch and reset generator are capable of generating reset signals to any device on the board Socketed oscillator for Processor Local Bus clock and P...

Страница 11: ...dware building blocks for almost any PCI 9054 design More than 75 of the board area provides many carefully selected prototyping footprints The thirty 30 surface mount footprints and three 3 BGA landscapes support industry leading 16 bit and 32 bit embedded processors and DSPs from Hitachi Motorola IDT TI IBM and Analog Devices Also the PLCC footprints and PQFP footprints cover various common pack...

Страница 12: ... bit 50 MHz Control Bus Address Bus Data Bus SRAM Controller Arbiter Chip Select Generator Synchronous SRAM 32K x 32 Controls Address POM Connector Oscillator Clock Generator EEPROM 5v 3 3v Converter Test Headers RS232 Interface Programmable Transceiver DB9 Male Connector Reset Circuitry 4 Status LEDs Socket for Flash ROM Footprints and prototype area CPLD Figure 3 1 PCI 9054RDK LITE Hardware Bloc...

Страница 13: ...d _ Available 3 2 PCI 9054 The PCI 9054 PCI I O Accelerator is the most advanced general purpose 32 bit 33 MHz PCI bus master device available in the market today It offers a robust PCI Specification v2 2 implementation enabling burst transfers up to 132 MB per second The PCI 9054 incorporates the industry leading PLX data transfer engine including two intelligent DMA channels programmable Direct ...

Страница 14: ...ssaging Complete messaging unit mailbox and doorbell registers Queue management pointers which can be used for message passing under the I2O protocol or a custom protocol 3 3 Serial EEPROM A socketed 2 Kbit serial EEPROM U6 is used in this RDK It is connected directly to the PCI 9054 and provides the configuration data to initialize the PCI 9054 after the system reset There are 88 bytes of pre pro...

Страница 15: ...500 LSW of Local Bus Big Little Endian Descriptor LMISC 7 0 BIGEND 7 0 24h 0000 MSW of Range for PCI to Local Expansion ROM EROMRR 31 16 26h 0000 LSW of Range for PCI to Local Expansion ROM EROMRR 15 0 28h 0000 MSW of Local Base Address Re map for PCI to Local Expansion ROM EROMBA 31 16 2Ah 0000 LSW of Local Base Address Re map for PCI to Local Expansion ROM EROMBA 15 0 2Ch 4343 MSW of Bus Region ...

Страница 16: ...pace 1 LAS1RR 31 16 4Ah 0000 LSW of Range for PCI to Local Address Space 1 LAS1RR 15 0 4Ch 2000 MSW of Local Base Address Re map for PCI to Local Address Space 1 LAS1BA 31 16 4Eh 0001 LSW of Local Base Address Re map for PCI to Local Address Space 1 LAS1BA 15 0 50h 0000 MSW of Bus Region Descriptors for PCI to Local Address Space 1 LBRD1 31 16 52h 01C3 LSW of Bus Region Descriptors for PCI to Loca...

Страница 17: ...gnal READY to terminate PCI 9054 memory cycles The external arbiter in the CPLD accepts two Processor Local Bus request signals LBR 1 0 and the bus request from the PCI 9054 LHOLD signal and it generates bus grant signals LBG 1 0 to the Processor Local Bus masters and LHOLDA to PCI 9054 chip Also the built in chip select generator in the CPLD provides four active low chip select signals to the dev...

Страница 18: ...ta Circuit Equipment DCE 3 8 2 Debug and Status LEDs There are four green user defined LEDs near the top edge of the RDK board The anode of each LED is connected to 3 3VDC through a 150 ohm watt resistor The cathode of each LED is connected to a prototyping pad for customer use As long as an active low signal can sink 16 20 mA of current it can directly drive the LEDs without changing the resistor...

Страница 19: ...signer wants to build a complex design on the Processor Local Bus there are enough footprints for CPU memory programmable control logic bus transceivers and discrete devices Table 3 4 Thirty 30 Surface Mount Footprints Package Quantity Pin Pitch Examples of Applications 16 pin SOIC 2 0 05 Discrete Logic 28 pin SOIC 2 0 05 Discrete Logic 28 pin PLCC 3 0 05 PALs 44 pin PLCC 1 0 05 CPLDs 44 pin PQFP ...

Страница 20: ... ironwoodelectronics com BGA Land Sockets and or Minigrid Sockets to convert from BGA to PGA and prototype a BGA chip on this RDK 2 Solder the BGA device on the top of the Land Socket and solder the Land Socket to the PC board If a designer uses the BGA3 landscape they have only one choice to buy Ironwood s BGA Land Socket Solder the BGA on the top of the Land Socket and solder the Land Socket to ...

Страница 21: ...ve for each mode are detailed in Table 3 5 Table 3 5 PCI 9054 Mode Setting Install R3 R4 R26 R27 R28 R29 R30 R42 R44 and R46 C Mode Do not install R1 R2 R22 R23 R24 R25 R31 R43 R45 and R47 LA29 resistor RN12 1 8 must be a pull up default configuration Default Install R1 R4 R26 R27 R28 R29 R30 R43 R45 and R47 J Mode Do not install R2 R3 R22 R23 R24 R25 R31 R42 R44 and R46 ALE resistor RN12 1 8 must...

Страница 22: ...access also requires successful arbitration and active clock LCLK Remove the 10K resistor R74 and install a 1K resistor at R19 Note If a programmed EEPROM is later added to the modified RDK the pull down must be changed back to a pull up Remove the 1K resistor at R19 and install a 10K resistor at R74 To modify the RDK to pull the READY input low a Lift from the board the Altera CPLD D15 READY pin ...

Страница 23: ... typing the dl HBuf command write 16 bit data 8888h to address s0 g Change the contents of the DMA scratch buffer db s0 1 el HBuf 99999999 read a byte from address s0 el HBuf 4 88888888 eb s0 88 el HBuf 8 77777777 write 8 bit data 88h to address s0 el HBuf c 66666666 2 DMA burst read write from to onboard SRAM el HBuf 10 55555555 a At the lower pane of PLXMon type Vars to obtain the addresses for ...

Страница 24: ......

Страница 25: ...ss strobe from 9054 BLAST_ burst last from 9054 LBE_ byte enable from 9054 LWDRD_ local bus read write ADDR_IN local bus address inputs ADDR_4MSBS local bus address A31 A28 READY_ ready signal to PLX PCI9054 address and control signals to synchronous SRAM SRAM_ADDR address outputs to the sync SRAM SRAMCS_ chip select to the SRAM SRAMOE_ output enable to the SRAM SRAM_BW_ byte enables in SRAM write...

Страница 26: ...RAM_ADDR reg 1 0 LBG reg LHOLDA reg SRAMCS_ reg SRAMOE_ internal variables reg 3 0 A31_28 reg 2 0 currentstate nextstate reg oer bufif0 READY_ oer oer chip selects Four most upper address lines A31 A28 are used to generate four chip select signals for the board They are CS 3 0 with address as CS_0 4000_0000h CS_1 5000_0000h CS_2 6000_0000h CS_3 7000_0000h wire 3 0 CS_ ADDR_4MSBS 4 b0100 4 b1110 AD...

Страница 27: ...BR 1 else LBG 1 0 always posedge CLK_50MHZ if LBR 1 LBR 0 LBG 0 LBR 0 else LBG 0 0 State definition parameter s0 4 b0000 idle parameter s1 4 b0001 cycle start parameter s2 4 b0010 single cycle wait state parameter s3 4 b0011 single cycle last state parameter s4 4 b0100 burst cycle wait state parameter s5 4 b0101 burst cycle repeat state parameter s6 4 b0110 burst cycle last state SRAM address coun...

Страница 28: ...DR_4MSBS casex currentstate s0 if ADS_ ADDR_4MSBS 4 b0010 nextstate s1 else nextstate s0 s1 if BLAST_ nextstate s2 else if BLAST_ nextstate s4 else nextstate s1 s2 nextstate s3 s3 if ADS_ nextstate s1 else nextstate s0 s4 nextstate s5 s5 if BLAST_ nextstate s5 else nextstate s6 s6 if ADS_ nextstate s1 else nextstate s0 endcase output logic ...

Страница 29: ...begin oer 1 SRAMCS_ 0 SRAMOE_ 1 end s2 begin oer 0 SRAMCS_ 0 if LWDRD_ 0 SRAMOE_ 0 else SRAMOE_ 1 end s3 begin oer 1 SRAMCS_ 1 SRAMOE_ 1 end s4 begin oer 0 SRAMCS_ 0 if LWDRD_ 0 SRAMOE_ 0 else SRAMOE_ 1 end s5 begin oer 0 SRAMCS_ 0 if LWDRD_ 0 SRAMOE_ 0 else SRAMOE_ 1 end s6 begin oer 1 SRAMCS_ 1 SRAMOE_ 1 end endcase always posedge CLK_50MHZ currentstate nextstate endmodule ...

Страница 30: ......

Страница 31: ... IC CPLD 64 IO pin 4ns delay 3 3V 100 pin TQFP Insight U9 5 1 Maxim MAX214CWI IC programmable DTE DCE RS232 transceiver 5V 28 pin wide SOP Digi Key U7 6 1 Maxim MAX6306UK30D1 T IC Reset Controller 1ms reset SOT23 5 Digi Key U8 7 1 Micron Technology MT58LC32K32B3LG 8 5 IC 1Mb Syncburst SRAM 32Kx32 8 5ns access time 100 pin TQFP Marshall U10 8 4 Hewlett Packard HSMG C650 LED green SMT SMT 1206 Digi ...

Страница 32: ...hm 5 SMT 0805 Digi Key R11 R15 28 1 Panasonic ERJ 6GEYJ392V Res 1 10W 3 9K 5 SMT 0805 Digi_key R74 29 13 Panasonic ERJ 6GEYJ102V Res 1 10W 1K 5 SMT 0805 Digi Key R52 R64 30 1 Panasonic ERJ 6GEYJ511V Res 1 10W 510 ohm 5 SMT 0805 Digi Key R18 31 4 Panasonic ERJ 6GEYJ151V Res 1 10W 150 ohm 5 SMT 0805 Digi Key R34 R37 MANUALLY INSERTED COMPONENTS 32 1 Ecliptek EP1345HSPD 50 000M OSC 50 MHz clock oscil...

Страница 33: ...F 50V 10 SMT 0805 Electrosonic C27 39 1 Ecliptek EP1345PD 50 000M OSC 50 MHz clock oscillator 3 3V 50ppm 40 60 duty cycle 14 pin full size DIP Ecliptek U4 40 1 AMP 520251 4 Modular jack assembly 8 position RJ45 PCB mounted Digi Key J4 41 1 Molex 87531 0001 USB receptacle 4 position type A PCB mounted Digi Key J5 SUBSTITUTE VENDOR AND PART LIST 1 1 Semtech EZ1587CM 3 3 IC 3A 5V to 3 3V LDO regulato...

Страница 34: ...PCI 9054RDK LITE Hardware Reference Manual v1 3 26 2006 PLX Technology Inc All rights reserved ...

Страница 35: ...al Block Diagram SRAM Controller PG 4 Test Headers PG 6 User Accessible RS232 Transceiver PG 4 Prototype Footprints PG7 PG12 JPOM Connector PG 5 001 002 5 3 1999 5 17 1999 Updated BOM Updated schematics and BOM Reset Circuit PG4 Updated the note on schematic 1 3 4 and the BOM 2 4 2002 003 PCI9054RDK LITE 003 PLX TECHNOLOGY INC 870 Maude Ave Sunnyvale CA 94085 Custom 1 13 Thursday October 21 2004 w...

Страница 36: ...CI_RST_L 3 PCI_CLK 3 PCI_REQ_L 3 PCI_GNT_L 3 PCI_IDSEL 3 PCI_SERR_L 3 PCI_FRAME_L 3 PCI_PME_L 3 5VCC 5VCC 5VCC 5VCC 3 3VCC 12V 12V T30 T31 T32 C23 10uF T44 U1 LT1587CM 3 3 VIN 3 GND 1 VOUT 2 T34 J1 PCICONUNV TRST A1 12V B1 12V A2 TCK B2 TMS A3 GND B3 TDI A4 TDO B4 5V A5 5V B5 INTA A6 5V B6 INTC A7 INTB B7 5V A8 INTD B8 RESERVED A9 PRSNT1 B9 VIO A10 RESERVED B10 RESERVED A11 PRSNT2 B11 3 3VAUX A14 ...

Страница 37: ... R8 0 C28 0 1uF R26 10K RN6 742 08 3 103 J XX 1 2 3 4 5 6 7 8 R14 22 RN5 742 08 3 103 J XX 1 2 3 4 5 6 7 8 U6 93CS56L or 66L 8DIP Socket CS 1 SK 2 DI 3 DO 4 VCC 8 PRE 7 PE 6 GND 5 R5 10K R6 10K R31 10K L1 Ferrite 500mA R18 510 PLX PCI9054 Universal C J M LD0 LAD0 LD31 LAD1 LD30 LAD2 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 ...

Страница 38: ... 0 1uF PB16 PB42 C59 0 1uF PB17 C74 0 01uF C60 0 1uF PB43 PB18 C75 0 01uF C61 0 1uF PB19 C76 0 01uF C62 0 01uF R38 10K PB20 C77 0 01uF C63 0 01uF R41 10K PB21 C64 0 01uF PB22 C65 0 01uF PB31 PB32 PB33 C53 1uF PB34 PB35 PB36 C57 1uF PB37 C55 1uF J2 DB9 Male Connector 5 9 4 8 3 7 2 6 1 C54 1uF R40 0 JP1 5X2 Header 1 2 3 4 5 6 7 8 9 10 R52 1K PB46 R53 1K R54 1K R55 1K R49 0 U9 EPM7064AE 5ns A1 14 A2 ...

Страница 39: ...NT LBE0 LBE1 LBE2 LBE3 BTERM LA 31 2 BREQi BREQo 12V 12V 5VCC 5VCC 3 3VCC PA5 R72 0 PA6 R73 0 PA8 PA7 R66 0 R65 0 PA2 R69 0 PA13 PA12 PA11 R70 0 J3 PLX Option Module 1 POM1 DMAREQ0 51 DMAACK0 52 DMAEOT0 53 DMAREQ1 54 DMAACK1 55 DMAEOT1 56 USER0 57 USER1 58 5 VCC 59 3 3 VCC 60 3 3 VCC 61 ASYNC_SEL 62 PPC_ALE_H 63 LABS2 64 LABS3 65 3 3 VCC 66 POM_SERR 67 5 VCC 68 DEN 69 DT R 70 3 3 VCC 71 RD_STRB 72...

Страница 40: ...i 3 U D Lo 3 MODE1 3 MODE0 3 LINT 3 D E 3 LRESET 3 4 WAIT 3 BREQi 3 BREQo 3 BLAST 3 4 LSERR 3 ADS 3 4 5 LHOLDA 3 4 LHOLD 3 4 DP0 3 LCLOCK 3 DP2 3 DP1 3 DP3 3 BTERM 3 LW R 3 4 READY 3 4 LBE0 LBE1 LBE3 LBE2 PK82 PK93 PK42 PK86 PK89 PK47 PK85 PK91 PK81 PK92 PK87 PK90 PK84 PK95 PK83 PK40 PK34 PK38 PK37 PK33 LAH2 Logic Analyzer Header 5V 1 CLK1 3 D14 5 D12 7 D10 9 D8 11 D6 13 D4 15 D2 17 D0 19 CLK2 2 D...

Страница 41: ...PC10 PE24 PF26 PF69 PC61 PF162 PF93 PC17 PE33 PF25 TB1 HEADER 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 FP7 28 Pin PLCC 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 PF136 PF70 PC53 PF161 PF89 PC2 PE30 PF27 PF134 PC55 PD33 PF95 PC4 PE29 PF28 PF133 PC54 P...

Страница 42: ...PG204 PG203 PG202 PG201 PG200 PG199 PG223 PG222 PG 1 240 9 PG32 PG141 PG93 PG193 PG20 PG142 PG78 PG194 PG43 PG143 PG69 PG195 PG28 PG144 PG89 PG196 100 Pin TQFP FP17 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 4...

Страница 43: ...PG94 PG201 PG202 PG203 PG204 PG205 PG206 PG207 PG208 PG209 PG210 PG211 PG212 PG213 PG214 PG215 PG216 PG217 PG218 PG219 PG220 PG 1 240 PG 1 240 8 FP20 144 Pin TQFP Footprint 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41...

Страница 44: ...H34 PH186 PH150 PH138 PH138 PH84 PH179 PH143 PH20 PH2 PH37 PH38 PH53 PH122 PH123 PH154 PH171 PH172 PH202 PH203 PH 1 208 11 PH21 PH132 PH71 PH182 PH1 PH133 PH51 PH183 PH47 PH134 PH97 PH184 PH32 PH135 PH82 PH185 PH20 PH136 PH70 PH186 PH43 PH137 PH93 PH187 PH28 PH138 PH78 PH188 PH19 PH139 PH69 PH189 PH39 PH140 PH89 PH190 PH18 PH141 PH68 PH191 PH3 PH142 FP23 80 Pin TQFP Footprint 1 1 2 2 3 3 4 4 5 5 6...

Страница 45: ... 71 72 72 73 73 74 74 75 75 76 76 77 77 78 78 79 79 80 80 81 81 82 82 83 83 84 84 85 85 86 86 87 87 88 88 89 89 90 90 91 91 92 92 93 93 94 94 95 95 96 96 97 97 98 98 99 99 100 100 101 101 102 102 103 103 104 104 105 105 106 106 107 107 108 108 109 109 110 110 111 111 112 112 113 113 114 114 115 115 116 116 117 117 118 118 119 119 120 120 121 121 122 122 123 123 124 124 125 125 126 126 127 127 128 ...

Страница 46: ...I60 PI125 PI126 PI127 PI128 PI129 PI130 PI131 PI132 PI133 PI134 PI135 PI136 PI137 PI138 PI139 PI140 PI141 PI142 PI143 PI144 PI145 PI146 PI147 PI148 PI149 PI150 PI151 PI152 PI153 PI154 PI155 PI156 PI 1 160 PI56 FP26 160 Pin PQFP Footprint 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 ...

Страница 47: ... c Through hole Ptrototype Area FP29 FP30 54 pin TSOP 54 pin TSOP JP1 208 144 80 pin QFP FP18 FP20 0 5mm pitch on the back 176 100 pin QFP FP24 FP25 0 5mm pitch on the back 128 pin 0 4mm pitch TQFP on the back RJ45 USB connectors Note 1 Control Signal Connector LAH5 2 Control Signal Connector LAH6 3 Data Bus Connector LAH3 4 Data Bus Connector LAH4 5 Address Bus Connector LAH1 6 Address Bus Connec...

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