PLX Technology PCI 9054RDK-LITE, Справочник по аппаратуре, Страница: 14 / 47

PCI 9054RDK- LITE Hardware Reference Manual v1.3
6 © 2006 PLX Technology, Inc. All rights reserved.
3.2.1 Direct Master
•
Support for all PCI cycle types including
Type 0 and Type 1 configuration cycles
•
Read pre-fetching
•
Burst-length control
•
Programmable FIFO Almost Full Flag
•
Unaligned transfer support
•
Dynamic Endian swapping
•
Write Delay
3.2.2 Direct Slave
•
Multiple independent address spaces
•
Dynamic Processor/Local Bus width control
•
Dynamic Endian swapping
•
Read pre-fetching
•
Processor/Local Bus latency timer
3.2.3 PCI Messaging
•
Complete messaging unit mailbox and
doorbell registers
•
Queue management pointers, which can be
used for message passing under the I
2
O
protocol or a custom protocol
3.3 Serial EEPROM
A socketed 2 Kbit serial EEPROM (U6) is used
in this RDK. It is connected directly to the PCI
9054 and provides the configuration data to
initialize the PCI 9054 after the system reset.
There are 88 bytes of pre-programmed
configuration data in the serial EEPROM, which
include device and functional information for
plug-and-play (PnP), PCI memory resource
allocation, and initial values of internal registers.
3.3.1 Serial EEPROM Contents
The PCI 9054RDK-LITE serial EEPROM
contains the programmed values listed in Table
3-2 and Table 3-3.