PDP-434CMX
146
1
2
3
4
1
2
3
4
C
D
F
A
B
E
Power and Ground Pins
Power Management Pins
Configuration Pins
Pin Name
No.
Type
Function
MODE
99
In
Mode Select Pin. Used to select between drop-in strap-selected operation, or register
programmable operation. To activate register-programmable operation, tie both pin 99 and pin 7
LOW.
HIGH=161B (Compatible) Mode – strap selections are used to set part operation. Internal
registers controlling non strap-selectable functions are reset to their default values.
LOW=1161 (Programmable) Mode – I
2
C registers are used to program part operation.
OCK_INV
100
In
ODCK Polarity. A LOW level selects normal ODCK output. A HIGH level selects inverted
ODCK output. All other output signals are unaffected by this pin. They will maintain the same
timing no matter the setting of OCK_INV pin
SCL
I
2
C Port Clock. When pins 99 and 7 are tied LOW, pin 100 functions as an I
2
C port input clock.
The slave I
2
C function does not ever try to extend cycles by pulling this pin low, so the pin
remains input-only at all times. This pin accepts 3.3V signaling only; it is not 5V-tolerant.
PIXS
4
In
Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using QE[23:0].
A HIGH level indicates two pixels (up to 48-bits) per clock mode using QE[23:0] for first pixel
and QO[23:0] for second pixel.
STAG_OUT#
7
In
Staggered Output. A HIGH level selects normal simultaneous outputs on all odd and even data
lines. A LOW level selects staggered output drive. This function is only available in two pixels per
clock mode.
I2C_MODE#
This pin must be tied LOW to put the receiver into I
2
C mode.
ST
3
In/Out
Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects LOW output
drive strength.
SDA
I
2
C Port Data. When pins 99 and 7 are tied LOW, pin 3 functions as an I
2
C port data I/O signal.
This pin accepts 3.3V signaling only; it is not 5V-tolerant.
HS_DJTR
1
In
HSYNC De-jitter. This pin enables/disables the HSYNC de-jitter function. To enable the HSYNC
de-jitter function this pin should be HIGH. To disable the HSYNC de-jitter function this pin should
be LOW.
Pin Name
No.
Type
Function
SCDT
8
Out
Sync Detect. A HIGH level is outputted when DE is actively toggling indicating that the link is
alive. A LOW level is outputted when DE is inactive, indicating the link is down. Can be
connected to PDO# to power down the outputs when DE is not detected. The SCDT output itself,
however, remains in the active mode at all times.
PDO#
9
In
Output Driver Power Down (active LOW). A HIGH level indicates normal operation. A LOW level
puts all the output drivers only (except SCDT and CTL1) into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground. PDO# is a sub-set of the PD#
description. The chip is not in power-down mode with this pin. SCDT and CTL1 are not tri-stated
by this pin.
PD#
2
In
Power Down (active LOW). A HIGH level indicates normal operation. A LOW level indicates
power down mode. During power down mode, all the output drivers are put into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
Additionally, all analog logic is powered down, and all inputs are disabled. Driving PD# LOW
disables all internal logic and outputs, including SCDT and clock detect functions; it also resets
all internal programmable registers to their default states.
Pin Name
No.
Type
Function
VCC
6, 38, 67
Power
Digital Core VCC, must be set to 3.3V.
GND
5, 39, 68
Ground
Digital Core GND.
OVCC
18, 29, 43, 57, 78
Power
Output VCC, must be set to 3.3V.
OGND
19, 28, 45, 58, 76
Ground
Output GND.
AVCC
82, 84, 88, 95
Power
Analog VCC must be set to 3.3V.
AGND
79, 83, 87, 89, 92
Ground
Analog GND.
PVCC
97
Power
PLL Analog VCC must be set to 3.3V.
PGND
98
Ground
PLL Analog GND.
