EN 50
3139 785 33120
8.
IC Description
TERMINAL
TYPE
I/O
DESCRIPTION
PHP NO.
TYPE
I/O
DESCRIPTION
14, 46, 47
Supply
–
Digital circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
21, 44, 45
Supply
–
Digital circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1
µ
F and
0.001
µ
F. Lower frequency 10
µ
F filtering capacitors are also recommended.
These supply terminals are separated from PLLVDD and AVDD inside the device to
provide noise isolation. They should be tied at a low-impedance point on the circuit
board.
38
39
CMOS
I/O
PLL filter terminals. These terminals are connected to an external capacitor to form
a lag-lead filter required for stable operation of the internal frequency multiplier PLL
running from the crystal oscillator. A 0.1
µ
F
±
10% capacitor is the only external
component required to complete this filter.
19
CMOS
I
Link interface isolation control input. This terminal controls the operation of output
differentiation logic on the CTL and D terminals. If an optional Annex J type isolation
barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should
be tied low to enable the differentiation logic. If no isolation barrier is implemented
(direct connection), or TI bus holder isolation is implemented, the ISO terminal
should be tied high to disable the differentiation logic. For additional information
refer to TI application note
Galvanic Isolation of the IEEE 1394-1995 Serial Bus,
SLLA011.
13
CMOS
I
Link power status input. This terminal monitors the active/power status of the link
layer controller and controls the state of the PHY-LLC interface. This terminal
should be connected through a 10-k
Ω
resistor either to the VDD supplying the LLC,
or to a pulsed output which is active when the LLC is powered (see Figure 9). A
pulsed signal should be used when an isolation barrier exists between the LLC and
PHY. (See Figure 10.)
The LPS input is considered inactive if it is sampled low by the PHY for more than
2.6
µ
s (128 SYSCLK cycles), and is considered active otherwise (that is, asserted
steady high or an oscillating signal with a low time less than 2.6
µ
s). The LPS input
must be high for at least 21 ns to guarantee that a high is observed by the PHY.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface
into a low-power reset state. In the reset state, the CTL and D outputs are held in
the logic zero state and the LREQ input is ignored; however, the SYSCLK output
remains active. If the LPS input remains low for more than 26
µ
s (1280 SYSCLK
cycles), the PHY-LLC interface is put into a low-power disabled state in which the
SYSCLK output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl
register bit is set to 1, and is considered inactive if either the LPS input is inactive
or the LCtrl register bit is cleared to 0.
48
CMOS
I
LLC request input. The LLC uses this input to initiate a service request to the
TSB41AB1. Bus holder is built into this terminal.
16
17
18
CMOS
I
Power class programming inputs. On hardware reset, these inputs set the default
value of the power class indicated during self-ID. Programming is done by tying
these terminals high or low. Refer to Table 9 for encoding.
NAME
DGND
DVDD
FILTER0
FILTER1
ISO
LPS
LREQ
PC0
PC1
PC2
PD
12
CMOS
I
Power-down input. A high on this terminal turns off all internal circuitry except the
cable-active monitor circuits, which control the CNA output (64-terminal PAP
package only). Asserting the PD input high also activates an internal pulldown on
the RESET terminal to force a reset of the internal control logic. (PD is provided for
legacy compatibility and is not recommended for power management in place of
IEEE 1394a-2000 suspend/resume LPS and C/LKON features.)
