Circuit Diagrams and PWB Layouts
107
7.
SSB: STi7100: Debug
V+
V-
VCC
C1+
C1-
C2+
T2
T1
IN
IN
OUT
OUT
GND
T1
C2-
R2
R1
T2
R1
R2
A
B
C
D
E
A
B
C
D
E
1AM0 B6
1AM2 D6
2AM0 A4
2AM1 A
3
2AM2 A5
2AM
3
B5
7AM0 A4
7AM1-1 C4
7AM1-2 E4
9AM0 D5
9AM1 C
3
9AM2 E4
FAM0 B5
S
T40 DEBUG LINK
S
TI7100: DEBUG
FAM9 E5
FAMA E5
FAMB E5
FAME E6
FAMJ D5
UART2
7
7
1
2
3
4
5
6
2AM4 B
3
3
AM0 D5
3
AM1 B
3
3
AM2 B5
3
AM
3
B5
3
AM7 C4
3
AM
8
E4
FAM2 B6
FAM
3
D5
FAM4 D5
FAM5 D5
FAM6 D5
FAM7 D5
FAM
8
D5
UART
1
2
3
4
5
6
FAM1 B5
10K
3
AM
8
3
AM0
33
R
7
8
9
FAM4
17
1
8
19
2
20
3
4
5
6
1AM2
1
10
11
12
1
3
14
15
16
5-147279-5
3
AM2
100R
10K
3
AM7
FAM
3
+
3
V
3
FAM2
2AM4
100n
2AM
3
100n
FAME
FAMB
FAM7
FAM5
3
71
4
4
FAM6
71
4
2
74LVC07APW
7AM1-2
74LVC07APW
7AM1-1
1
100R
3
AM
3
FAM1
9AM2
FAM0
+
3
V
3
+
3
V
3
7
2
6
16
2AM2
100n
4
5
15
1
3
12
8
9
11
14
10
Φ
R
S
2
3
2
S
T
3
2
3
2C
7AM0
1
3
9AM1
FAMA
3
AM1
100R
2AM0
100n
+
3
V
3
FAM
8
FAM9
100n
2AM1
9AM0
RE
S
1
2
3
4
5
1AM0
B
3
B-PH-
S
M4-TBT(LF)
+
3
V
3
FAMJ
JTAG-TDI-
S
T
JTAG-TDO-
S
T
R
S
T-TARGETn
JTAG-TR
S
Tn-
S
T
TRIG-OUT
TRIG-IN
JTAG-TM
S
-
S
T
A
S
EBRKn
JTAG-TCK-
S
T
RXD-A
S
C2
TXD-A
S
C2
BUF-R
S
T-TARGETn
3
1
3
9 12
3
6214.4
I_17660_012.ep
s
110
3
0
8
B0
3
F
B0
3
F