102
7.
Circuit Diagrams and PWB Layouts
SSB: STi7100: Control
NC
GND
R
S
T
IN
CD
1
1
1
1
1
1
S
Y
S
B
S
Y
S
A
TXP
TXN
RXP
RXN
REF
ATA
CLKIN
DP
DM
REF
C1A
C2A
BYTECLK
BYTECLKVALID
PACKETCLK
ERROR
BYTECLK
BYTECLKVALID
ERROR
PACKETCLK
T
S
IN1
T
S
IN1DATA
0
1
2
3
4
5
6
7
BYTECLK
BYTECLKVALID
ERROR
PACKETCLK
T
S
IN2
T
S
IN2DATA
4
5
6
7
PIO5
0
1
2
3
4
5
6
7
PIO4
0
1
2
3
4
5
TRIGGER
S
Y
S
ITRQ
T
S
IN0
T
S
IN0DATA
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
PIO1
0
1
2
3
4
5
6
7
PIO0
U
S
B
DAA
0
1
2
3
4
5
6
7
0
1
2
3
S
Y
S
BCLKO
S
C
S
Y
S
BCLKINALT
S
Y
S
CLKOUT
RTCCLKIN
TMUCLK
R
S
ETIN
WDOGR
S
TOUT
A
S
EBRK
IN
OUT
0
1
2
3
NMI
TDI
TM
S
TCK
TR
S
T
TDO
6
7
PIO
3
0
1
2
3
4
5
6
7
PIO2
E
11
F
G
H
I
1A10 C4
2A1
8
B2
3
A02 D12
3
A01 D12
3
A1
3
-1 C9
3
A1
3
-2 C7
3
A1
3
-
3
C9
3
A1
3
-4 C7
3
A14 B9
3
A16 B7
3
A1
8
B9
RE
S
ERVED
1
2
3
4
5
6
7
8
9
10
11
12
1
3
1
10
12
1
3
A
B
C
D
E
MODE[15]
Re
s
erved
F
G
2A19 B2
2A20 B
3
2A21 C6
2A22 D
3
2A2
3
D4
2A24 F12
2A25 G12
2A26 G6
3
A19 H1
3
A20-1 A9
3
A20-2 A9
3
A20-
3
A9
3
A20-4 A9
3
A21 G
3
2
3
4
5
6
7
8
9
MODE[9:
8
]
3
A2
8
C4
3
A29-1 E
3
3
A29-2 E
3
3
A29-
3
F
3
3
A29-4 E
3
3
A
3
0-1 F
3
3
A
3
0-2 F
3
H
I
A
B
C
D
Mode pin
MODE[10]
EMIADDR[10:9]
S
Tx71000 m
as
ter/
s
l
a
ve mode
PCMOUT
3
MODE[
3
:2]
3
A
3
2-
3
H
3
3
A
33
B11
3
A
3
4 F12
3
A
3
5 H
3
3
A
3
6-1 H
3
3
A
3
6-2 H
3
3
A25-1 C
8
3
A25-2 C9
3
A25-
3
C
8
3
A25-4 C9
3
A26 C6
3
A27 C4
MODE[7:4]
EMIADDR[2:1]
PLL1
s
t
a
rt
u
p config
u
r
a
tion
PLL0
s
t
a
rt
u
p config
u
r
a
tion
Re
s
erved
3
A
3
0-
3
F
3
3
A
3
0-4 F
3
3
A
3
1-2 G
3
3
A
3
1-
3
G1
3
A
3
1-4 H
3
3
A
3
2-1 G
3
MODE[12:11]
MODE[1:0]
Re
s
erved
MODE[16]
EMI
ba
nk
s
port
s
ize
a
t
b
oot
Re
s
erved
P
u
rpo
s
e
PCMOUT2
Long re
s
eto
u
t mode
S
TI7100: CONTROL
EMIADDR[14]
3
A40-1 E7
3
A40-2 E7
3
A40-
3
E7
3
A41-1 E7
3
A41-2 E7
3
A41-
3
E7
3
A
3
7-1 D7
3
A
3
7-2 D7
3
A
3
7-
3
D7
3
A
38
-1 D7
3
A
38
-2 D7
3
A
38
-
3
D7
EMIADDR[15]
Re
s
erved
EMI pin
MODE[1
3
]
3
A45 D12
3
A46-1 B7
3
A46-2 B7
3
A46-
3
B6
3
A46-4 B6
3
A47 G5
3
A4
8
G5
5A10 A2
7A00-4 A10
7A10-1 C
3
3
A
38
-4 D7
3
A
3
9-1 D7
3
A
3
9-2 D7
3
A
3
9-
3
D7
3
A
3
9-4 D7
IA25 D11
PCMOUT4
MODE[14]
EMIADDR[
8
:5]
EMIADDR[1
3
:12]
7A12 C4
3
A41-4 E7
3
A42-1 E7
3
A42-2 E7
3
A42-
3
E7
3
A42-4 E7
3
A44 D11
EMIADDR[4:
3
]
FA11 B9
FA12 G6
IA10 C9
IA11 D9
IA12 F12
IA16 C4
IA17 C5
IA1
8
D4
IA19 A
3
IA20 C
3
IA21 C5
IA22 C6
IA2
3
B11
7A10-2 C4
7A10-
3
C6
7A10-4 C2
7A10-5 C2
7A10-6 D2
7A11 G6
IA27
IA26 G11
IA27 G11
IA2
8
F11
IA29 G6
IA
3
0 G7
9A21 C5
9A22 C5
9A2
3
G7
9A24 H7
9A25 F12
FA10 C7
3
A
3
9-
3
33
R
6
3
5
4
7
2
33
R
3
A
3
9-4
33
R
3
A
38
-2
10K
3
A29-
3
3
6
3
A
38
-1
33
R
8
1
3
A
3
1-
3
10K
3
A40-2
33
R
2
7
1n0
2A20
2A19
100n
100n
2A1
8
4
5
+2V5
+
3
V
3
10K
3
A
3
1-4
3
A01
10K
100R
3
A45
100R
3
A44
5
3
2
4
1
FA12
7A11
NCP
3
0
3
L
S
N10T1
IA26
9A24
V_LVC04
1
+
3
V
3
3
A14
22R
3
A1
3
-1
10K
3
A25-4
4
5
3
6
10K
3
6
3
A25-
3
10K
8
3
A41-
3
33
R
3
A42-1
33
R
1
33
R
3
A40-1
1
8
+
3
V
3
RE
S
3
A19
10K
3
A
3
4
470R
1
8
p
2A2
3
RE
S
7A10-
3
74LVCU04APW
5
71
4
6
6
3
3
A
3
7-
3
33
R
3
A
38
-4
33
R
5
4
+
3
V
3
9A2
3
2A26
100n
3
A4
8
1K2
V_LVC04
V_LVC04
3
A47
2K2
+
3
V
3
1
8
3
A25-1
10K
IA2
3
IA25
3
A02
100R
IA
3
0
5
IA29
10K
3
A29-4
4
IA22
IA21
10K
3
A
3
0-2
10K
2
7
3
A16
1
8
6
3
10K
3
A
3
0-1
7
2
33
R
3
A
38
-
3
33
R
3
A
3
7-2
11
71
4
10
2
7A10-5
74LVCU04APW
7A10-1
74LVCU04APW
1
71
4
3
A
3
2-1
10K
1
8
27M
1A10
RE
S
3
6
3
A
3
2-
3
10K
+
3
V
3
RE
S
2
7
IA20
6
3
A20-2
10K
3
A1
3
-
3
10K
3
2
7
IA1
8
10K
3
A29-2
IA17
IA16
5
10K
3
A46-4
8
1
7
2
33
R
3
A
3
7-1
1
3
A
3
9-2
33
R
10K
3
A46-1
10K
3
A
3
0-
3
3
6
IA11
2A22
1
8
p
RE
S
10K
3
A
3
5
10K
3
A20-
3
RE
S
6
3
IA2
8
IA10
33
R
3
A
3
9-1
8
1
V_LVC04
27M
2560TK
2
1
4
3
+
3
V
3
15p
7A12
2A21
2A24
10K
3
A
3
6-1
1
8
10n
2
7
V_LVC04
3
A
3
6-2
10K
220R
5A10
10K
3
A25-2 2
7
3
6
33
R
3
A42-
3
4
5
10K
3
A1
3
-4
3
A2
8
560R
RE
S
9A22
2A25
10n
9A25
FA11
74LVCU04APW
1
3
71
4
12
3
71
4
4
7A10-6
8
7A10-2
74LVCU04APW
7A10-4
74LVCU04APW
9
71
4
FA10
3
A27
1M0
RE
S
3
A
33
1K5
33
R
3
A40-
3
3
6
3
A26
6
8
R
2
7
+
3
V
3
10K
3
A
3
1-2
10K
3
A1
8
3
A42-2
33
R
2
7
IA19
33
R
3
A41-4
4
5
3
A41-2
33
R
2
7
33
R
3
A41-1
1
8
9A21
RE
S
RE
S
8
1
IA12
54
3
A20-1
10K
10K
3
A20-4
RE
S
6
3
A46-
3
10K
10K
3
A46-2
7
3
A
3
0-4
10K
4
5
E19
3
A21
10K
AM2
AM1
AL2
AL1
AL
3
AP2
AP
3
AP25
AN25
AM25
AC5
AB4
AB5
AA4
AE4
AF4
AM
3
AN
3
AP1
AN2
AN1
AH1
AH2
AH4
AJ4
AG5
AF5
AE5
AD4
AD5
AC4
E1
8
D17
D1
8
AK6
AJ5
AH5
AG4
AK1
AK2
AJ1
AJ2
E27
AN27
E17
AK25
AK26
AK27
AK2
8
D21
D22
E22
E21
AA
3
4
AA
33
Y
3
4
Y
33
AA
3
1
Y
3
0
Y
3
1
D16
C1
AP27
AC
33
AB
3
4
AD
3
2
AD
3
0
AD
3
1
AC
3
0
AC
3
1
AB
3
0
AB
3
1
AA
3
0
AB
33
AH
3
1
AG
3
0
AG
3
1
AE
3
1
AE
3
0
AE
3
2
AE
3
4
AE
33
AD
3
4
AD
33
AC
3
4
AL
33
AK
3
4
AK
33
AJ
3
4
AJ
33
AH
3
4
AH
33
AJ
3
0
AJ
3
1
AH
3
0
D19
D20
AM
3
2
AP
33
AN
33
AP
3
4
AN
3
4
AM
33
AM
3
4
AL
3
2
AL
3
4
AM
3
0
AP
3
1
AN
3
1
AP
3
0
AN
3
0
AN5
AP5
E16
E20
2
7
7A00-4
S
TI7100YWC
Φ
DIGITAL
INTERFACE
10K
3
A1
3
-2
4
5
1
8
33
R
3
A42-4
3
A29-1
10K
TRIG-IN
JTAG-TM
S
-
S
T
JTAG-TCK-
S
T
JTAG-TR
S
Tn-
S
T
JTAG-TR
S
Tn-
S
T
JTAG-TCK-
S
T
JTAG-TM
S
-
S
T
JTAG-TDI-
S
T
WP-FLA
S
H-
S
T
R
S
ETIN-
S
T7100
RE
S
ET-
S
T7100
BUF-R
S
T-TARGETn
R
S
ETIN-
S
T7100
S
T-DL-APP
S
DA-
SS
B
T
S
I1-
S
T-
S
TRT
T
S
I0-
S
T-D0
T
S
I0-
S
T-D1
T
S
I0-
S
T-D2
T
S
I0-
S
T-D
3
T
S
I0-
S
T-D4
T
S
I0-
S
T-D5
T
S
I0-
S
T-D6
T
S
I0-
S
T-D7
T
S
I1-
S
T-D0
T
S
I1-
S
T-D1
T
S
I1-
S
T-D2
T
S
I1-
S
T-D
3
T
S
I1-
S
T-D4
T
S
I1-
S
T-D5
T
S
I1-
S
T-D6
T
S
I1-
S
T-D7
PCMOUT2
PCMOUT
3
CA-MICLK
T
S
I0-
S
T-CLK
CA-MIVAL
T
S
I0-
S
T-VAL
CA-MI
S
TRT
T
S
I0-
S
T-
S
TRT
CA-MDI0
CA-MDI1
CA-MDI2
CA-MDI
3
CA-MDI4
CA-MDI5
CA-MDI6
CA-MDI7
CA-MOCLK_V
S
2
CA-MOVAL
CA-MO
S
TRT
CA-MDO0
CA-MDO1
CA-MDO2
CA-MDO
3
CA-MDO4
CA-MDO5
CA-MDO6
CA-MDO7
T
S
I1-
S
T-D5
T
S
I1-
S
T-CLK
T
S
I1-
S
T-VAL
EMI-A
3
EMI-A
8
EMI-A7
EMI-A6
EMI-A5
EMI-A10
EMI-A9
PCMOUT4
EMI-A1
3
EMI-A12
EMI-A14
EMI-A15
EMI-A4
EMI-A1
EMI-A2
27MHZ-
3
V
3
EMI-A14
TMUCLK
CPU-27MHZ
RXD-A
S
C2
TXD-A
S
C2
JTAG-TDI-
S
T
JTAG-TDO-
S
T
JTAG-TDO-
S
T
T
S
I0-
S
T-CLK
T
S
I0-
S
T-VAL
T
S
I0-
S
T-D0
T
S
I0-
S
T-D1
T
S
I0-
S
T-D2
T
S
I0-
S
T-D
3
T
S
I0-
S
T-D4
T
S
I0-
S
T-D5
T
S
I0-
S
T-D6
T
S
I0-
S
T-D7
T
S
I0-
S
T-
S
TRT
T
S
I1-
S
T-CLK
T
S
I1-
S
T-VAL
T
S
I1-
S
T-D0
T
S
I1-
S
T-D1
T
S
I1-
S
T-D2
T
S
I1-
S
T-D
3
T
S
I1-
S
T-D4
T
S
I1-
S
T-D6
T
S
I1-
S
T-D7
T
S
I1-
S
T-
S
TRT
S
CL-
SS
B
A
S
EBRKn
CPU-27MHZ
TMUCLK
TRIG-IN
TRIG-OUT
27MHZ-
3
V
3
3
1
3
9 12
3
6214.4
I_17660_007.ep
s
110
3
0
8
B0
3
A
B0
3
A