64
7.
Circuit Diagrams and PWB Layouts
SSB: FPGA I/O Banks
CLK
M
S
EL
6
5
4
3
2
1
0
7
DATA0
DCLK
TDI
TDO
TM
S
TCK
1
0
CONF_DONE
CONFIG
S
TATU
S
CE
NC
NC
VCCA_PLL
VCCD_PLL
GNDA_PLL
GND
GND
GND
VCCIO4
VCCINT
1
2
1
2
2
1
GND_PLL2
GND_PLL1
VCCIO
3
VCCIO2
VCCIO1
4
5
6
2706 C2
8
A
F
11
E
NC
C
K
NC
C
B
6
J
K
9
1
3
L
J
D
E
10
G
7
11
G
I
12
I
H
4
7
8
NC
3
722 B11
3
72
3
C11
3
724 C11
3
74
3
D7
L
10
2701 B2
2702 B4
B
NC
FPGA I/O BANK
S
RE
S
F
NC
NC
3
I72
8
H
3
4701 G11
3
742 D7
F706 G10
3
744 D7
2
3
72
8
D11
3
729 D11
270
3
B4
14
15
3
725 C11
3
7
3
9 C7
1
3
3
749 B7
1
3
7
38
B7
570
3
D2
7700-5 C9
271
3
C5
3
7
3
1 D11
3
7
3
2 E11
3
74
8
B7
2704 B5
F7
3
4 G10
3
701 F11
3
750 G7
3
7
33
E11
F705 F2
7700-4 I14
3
7
3
6 C7
F704 E
3
F70
3
D2
I729 G10
3
746 D7
3
702 G11
I7
3
0 G11
2715 C5
3
726 C11
2700 I2
27
3
0 F
3
2714 C5
3
727 C11
2719 D
3
7700-1 F9
4700 F11
2725 E
3
5700 B2
3
747 B7
2707 C
3
9
2709 C
3
2710 C4
12
16
17
A
H
3
721 B11
5
3
INPUT BANK
2721 D4
RE
S
NC
NC
2729 F
3
NC
OUTPUT BANK
RE
S
15
D
17
1
2
F7
33
G10
5704 E2
F702 C2
3
741 D7
2726 E4
3
752 G7
3
700 F10
5705 E
3
2711 C4
3
70
3
F10
14
F701 B2
3
720 B11
2717 D2
271
8
D
3
3
7
3
7 C7
2720 D
3
270
8
C
3
2724 E
3
I712 H5
3
740 C7
27
3
4 H
8
7700-6 E15
5702 D2
2705 B5
I71
3
H
3
16
3
7
3
5 C7
3
71
3
G7
3
714 G7
2712
3
0R
5704
3
7
3
4 E11
3
751 G7
7700-7 I16
3
75
3
G7
2712 C4
3
7
3
0 D11
I705 H5
3
745 D7
7700-2 G4
7700-
3
H12
5701 C2
1
8
0R
3
7
38
22R
3
74
8
3
714
1
8
0R
1
8
0R
3
724
F706
22R
1
8
0R
3
7
3
6
3
746
2715
10n
22R
3
750
+1V2-PLL
+
3
V
3
_FPGA
FPGA_BL_DIMMING
3
7
3
2
22R
3
722
22R
2700
1n0
22R
3
744
3
742
+
3
V
3
_FPGA
I712
1
8
0R
I71
3
2729
1
u
0
1
8
0R
3
7
33
22R
3
7
3
4
22R
3
74
3
3
7
3
0
1
8
0R
22R
3
740
+1V2_
S
W
F702
22R
3
7
3
5
3
720
22R
F7
3
4
3
75
3
22R
3
721
1
8
0R
3
0R
5702
570
3
3
0R
10K
3
701
10n
270
3
+
3
V
3
_FPGA
2702
10n
3
751
22R
10K
3
70
3
+2V5in-FPGA
+
3
V
3
_FPGA
F704
27
3
4
1n0
1
8
0R
3
7
3
7
3
7
3
9
22R
F7
33
2726
10n
2706
4
u
7
22R
3
7
3
1
3
72
8
22R
22R
3
726
+2V5_
S
W
22R
3
72
3
+2V5in-FPGA
22R
3
752
FPGA_BL_BOO
S
T
10n
10n
+1V2-FPGA
2714
22R
3
749
3
747
22R
F701
1
8
0R
3
745
3
741
22R
F2
H5
G2
G1
I705
H15
J15
J16
J5
L1
3
F1
H4
J1
3
K12
M1
3
EP2C5F256C7N
G5
H2
H1
J2
J1
H16
7700-1
CONTROL
Φ
IO_T
8
|LVD
S
5
3
p
T9
IO_T9|LVD
S
52p
I72
8
IO_T12|LVD
S
46p
T1
3
IO_T1
3
|LVD
S
45p
T14
IO_T14|LVD
S
44p
T
3
IO_T
3
|LVD
S
5
8
p
T4
IO_T4|LVD
S
56p
T5
IO_T5|LVD
S
55p
T6
IO_T6
T7
IO_T7|LVD
S
54p
T
8
IO_R
3
|LVD
S
5
8
n
R4
IO_R4|LVD
S
56n
R5
IO_R5|LVD
S
55n
R7
IO_R7|LVD
S
54n
R
8
IO_R
8
|LVD
S
5
3
n
R9
IO_R9|LVD
S
52n
T10
IO_T10|LVD
S
49n
T11
IO_T11|LVD
S
51p
T12
IO_P1
3
|LVD
S
47n
P4
IO_P4|LVD
S
57n
P5
IO_P5|LVD
S
57p
R10
IO_R10|LVD
S
49p
R11
IO_R11|LVD
S
51n
R12
IO_R12|LVD
S
46n
R1
3
IO_R1
3
|LVD
S
45n
R14
IO_R14|LVD
S
44n
R
3
IO_L9|LVD
S
50p
M11
IO_M11|LVD
S
4
3
p
N10
IO_N10|LVD
S
59n
N11
IO_N11|VREFB4N0
N
8
IO_N
8
|VREFB4N1
N9
IO_N9|LVD
S
59p
P11
IO_P11
P12
IO_P12|LVD
S
47p
P1
3
K10
IO_K10|LVD
S
4
8
n
K11
IO_K11|LVD
S
4
8
p
L10
IO_L10|LVD
S
50n
L11
IO_L11|LVD
S
4
3
n
L12
IO_L12
L7
IO_L7|LVD
S
60p
L
8
IO_L
8
|LVD
S
60n
L9
7700-5
EP2C5F256C7N
Φ
BANK4
10n
2725
3
729
+1V2-FPGA
22R
3
725
+2V5o
u
t-FPGA
22R
2705
+
3
V
3
_
S
W
10n
1
8
0R
10n
3
71
3
10n
2719
2710
2717
4
u
7
5705
3
0R
I7
3
0
2721
10n
2711
M7
P10
P7
T15
T2
10n
A15
A2
C10
C7
E10
E7
B16
G14
K14
R16
M10
E12
L6
F11
G9
H10
H7
J7
B1
G
3
K
3
R1
E
8
E9
G
8
M6
E11
L5
N5
D12
F12
M5
P
8
P9
R15
R2
T1
T16
B15
B2
C
8
C9
H
3
H
8
H9
J14
J
3
J
8
J9
K9
M
8
A16
M9
EP2C5F256C7N
Φ
POWER
7700-6
A1
H14
I729
D9
E1
3
E15
+2V5o
u
t-FPGA
K
8
N
3
N4
N6
N7
P6
R6
C16
D1
D2
D7
F14
F5
G4
H6
J10
J6
K1
3
K6
K7
C15
Φ
NC
EP2C5F256C7N
7700-7
B
8
F1
3
IO_P
3
P
3
3
700
10K
IO_M1
M1
IO_M2
M2
IO_M
3
M
3
IO_M4|PLL1_OUTn
M4
IO_N1|LVD
S
1 p
N1
IO_N2|LVD
S
1 n
N2
IO_P1|LVD
S
0 p
P1
IO_P2|LVD
S
0 n
P2
IO_K1|LVD
S
4 n
K1
IO_K2|LVD
S
4 p
K2
IO_K4|LVD
S3
p
K4
IO_K5|LVD
S3
n
K5
IO_L1|LVD
S
2 p
L1
IO_L2|LVD
S
2 n
L2
IO_L
3
L
3
IO_L4|PLL1_OUTp
L4
E1
IO_E1|LVD
S
5 p
E2
IO_E2|LVD
S
5 n
IO_E
3
|LVD
S
7 p
E
3
IO_E4|LVD
S
7 n
E4
IO_E5|LVD
S8
n
E5
IO_F
3
|VREFB1N0
F
3
IO_F4|C
S
O_
F4
IO_J4|VREFB1N1
J4
IO_C1|LVD
S
9 p
C1
C2
IO_C2|LVD
S
9 n
IO_C
3
|A
S
DO
C
3
IO_D
3
|LVD
S
6 p
D
3
IO_D4|LVD
S
6 n
D4
IO_D5|LVD
S8
p
D5
Φ
BANK1
EP2C5F256C7N
7700-2
F9
IO_F9|LVD
S
12p
G10
IO_G10|LVD
S
24n
G11
IO_G11|LVD
S
24p
G6
IO_G6|LVD
S
11n
G7
IO_G7|LVD
S
11p
F705
D11
IO_D11|LVD
S
22n
D6
IO_D6|LVD
S
17n
D
8
IO_D
8
|VREFB2N1
E6
IO_E6|LVD
S
1
3
p
F10
IO_F10|LVD
S
12n
F6
IO_F6|LVD
S
1
3
n
F7
IO_F7|LVD
S
19n
F
8
IO_F
8
|LVD
S
19p
B9
IO_B9|LVD
S
21p
C11
IO_C11|VREFB2N0
C12
IO_C12|LVD
S
27p
C1
3
IO_C1
3
|LVD
S
27n
C4
IO_C4|LVD
S
10p
C5
IO_C5|LVD
S
10n
C6
IO_C6|LVD
S
17p
D10
IO_D10|LVD
S
22p
B12
IO_B12|LVD
S
25n
IO_B1
3
|LVD
S
26n
B1
3
B14
IO_B14|LVD
S
2
8
n
B
3
IO_B
3
|LVD
S
14n
B4
IO_B4|LVD
S
15n
B5
IO_B5|LVD
S
16n
B6
IO_B6|LVD
S
1
8
n
B7
IO_B7|LVD
S
20p
A5
IO_A5|LVD
S
16p
A6
IO_A6|LVD
S
1
8
p
A7
IO_A7|LVD
S
20n
A
8
IO_A
8
A9
IO_A9|LVD
S
21n
B10
IO_B10|LVD
S
2
3
n
B11
IO_B11
A10
IO_A10|LVD
S
2
3
p
A11
IO_A11
A12
IO_A12|LVD
S
25p
A1
3
IO_A1
3
|LVD
S
26p
A14
IO_A14|LVD
S
2
8
p
A
3
IO_A
3
|LVD
S
14p
A4
IO_A4|LVD
S
15p
7700-
3
EP2C5F256C7N
Φ
BANK2
5700
3
0R
271
3
10n
271
8
10n
2704
3
0R
10n
IO_N16|LVD
S3
9p
P14
IO_P14
P15
IO_P15|LVD
S
40n
P16
IO_P16|LVD
S
40p
5701
IO_M12|LVD
S
42p
M14
IO_M14|VREFB
3
N1
M15
IO_M15|LVD
S38
n
M16
IO_M16|LVD
S38
p
N12
IO_N12|LVD
S
42n
IO_N1
3
|LVD
S
41n
N1
3
IO_N14|LVD
S
41p
N14
N15
IO_N15|LVD
S3
9n
N16
IO_H1
3
|VREFB
3
N0
J11
IO_J11|LVD
S3
2n
J12
IO_J12|LVD
S3
5p
K15
IO_K15|LVD
S3
6p
IO_K16|LVD
S3
6n
K16
IO_L14
L14
L15
IO_L15|LVD
S3
7n
L16
IO_L16|LVD
S3
7p
M12
IO_F15|LVD
S33
n
F16
IO_F16|LVD
S33
p
G12
IO_G12|LVD
S3
1n
G1
3
IO_G1
3
|LVD
S3
1p
G15
IO_G15|LVD
S3
4p
IO_G16|LVD
S3
4n
G16
H11
IO_H11|LVD
S3
2p
H12
IO_H12|LVD
S3
5n
H1
3
7700-4
C14
IO_C14|LVD
S
29n
D1
3
IO_D1
3
|LVD
S
29p
D14
IO_D14|PLL2_OUTn
IO_D15|LVD
S3
0n
D15
IO_D16|LVD
S3
0p
D16
IO_E14|PLL2_OUTp
E14
IO_E16
E16
F15
EP2C5F256C7N
Φ
BANK
3
1
8
0R
3
727
2707
+1V2-PLL
10n
1
u
0
2701
47
u
3
702
10K
F70
3
4V
2724
27
3
0
10n
2720
10n
4701
10n
270
8
2709
10n
4700
TxFPGAo_CLKn
TxFPGAe_CLKp
TxFPGAe_CLKn
TxFPGAo_4n
TxFPGAo_
3
p
TxFPGAo_
3
n
TxFPGAo_CLKp
TxFPGAo_1p
TxFPGAo_1n
TxFPGAo_2p
TxFPGAo_2n
TxFPGAo_4p
TxFPGAe_0p
TxFPGAe_0n
TxFPGAe_4p
TxFPGAe_4n
TxFPGAo_0p
TxFPGAo_0n
TxFPGAe_
3
n
TxFPGAe_2p
TxFPGAe_2n
TxFPGAe_1p
TxFPGAe_1n
TxFPGAe_
3
p
CLK_O
S
C1
MAIN_
S
CL
TDO_FPGA
TDI_FPGA
DATA0
TCK_FPGA
DCLK
TM
S
_FPGA
AMBI_
S
DA
a
m
b
i_pwm(
3
)
a
m
b
i_pwm(2)
a
m
b
i_pwm(5)
MAIN_
S
DA
AMBI_
S
CL
a
m
b
i_pwm(0)
a
m
b
i_pwm(1)
A
S
DO
a
m
b
i_pwm(4)
nC
S
O
B04D
B04D
I_17760_00
8
.ep
s
1
8
020
8
3
1
3
9 12
3
6
3
49.1
Содержание 47PFL5403
Страница 26: ...Service Modes Error Codes and Fault Finding EN 26 LC8 2A LA 5 Personal Notes E_06532_012 eps 131004 ...
Страница 43: ...Circuit Diagrams and PWB Layouts 43 LC8 2A LA 7 Layout Main Power Supply 42 Top Side H_16750_070 eps 110108 ...
Страница 44: ...44 LC8 2A LA 7 Circuit Diagrams and PWB Layouts Layout Main Power Supply 42 Bottom Side H_16750_071 eps 110108 ...
Страница 92: ...92 LC8 2A LA 7 Circuit Diagrams and PWB Layouts Personal Notes E_06532_013 eps 131004 ...