Philips 47PFL5403, Руководство по обслуживанию

Страница: 61 / 115

Circuit Diagrams and PWB Layouts 61 LC8.2A LA 7.
SSB: Trident WX69
NC
14 1 3
TRIDENT - WX69
1
2
1(HIGH)
T
O
FPGA /
T
O
L
V
D
S
CONNECT
OR
NC
RE S
0R
1 8
NC
RE
S
S INGLE 12NC : 3 1 3 9_12 3 _6 3 491
L
M M
RE
S
12
RE S
0(LOW)
L
NC
RE
S
RE
S
NC
MULTI 12NC : 3 1 3 9_12 3 _6 3 4 8 1
K
2
I
A
3
10
RE
S
K
8
5
RE
S
17 9
RE S
11
15 16
4
H
G
7
I
J
S CK Y11 I2C S l a ve Addre ss =0x7E/7F( * ) I2C S l a ve Addre ss =0x7C/7 D
NC
Pin N a me
S D0 V12 U s e Ri s ing Edge of WR# to l a tch d a t a ( * ) U s e F a lling Edge of WR# to l a tch d a t a
B
0(LOW)
RE S
RE S
1 3 12 6
NC
RE S
RE
S
RE S
DP_H S P19 MPU in A/D M u ltiplix Mode MPU in A/D S ep a r a te Mode( * )
19
NC
N
W S U12 U s e ALE to l a tch Addre ss U s e F a lling Edge s of WR#&RD# to l a tch Addre ss ( * )
NC
NC
B
5
N
D
F
O
1
O
P
E
F
8
RE
S
NC
NC
1 8
7
J
RE S
NC
3
Pin No
20
14
NC
"C00-"C99" & "V00 - V99"
A
D
E
NC
C
NC
20 19
G
NC
Pin No
1(HIGH)
6 17
H
C
15 16
9 4 10 11
P
Pin N a me
FC07
2C69
10 u
FC05
C? 100n
FC04
FC11
IC04
2V05
33
p
IC0 3
3
C49
FC06
33
p
2V04
FC09
FC10
FC0 8
+2V5_VDDMQ
3 V04
100R
IC05
+ 3 V 3 _ S W
+1V2_ADC
100n
2C
38
4K7
3
C47
2C65
470p
100n
2C54
+1V2_PLL
2C
3
4
22
u
6.
3
V
IC10
IC11
IC12
IC09
100n
2C76
+1V2_ADC
2C45
10
u
6.
3
V
2C46
10
u
6.
3
V
2C56
10
u
6.
3
V
33 R
5C19
100n
2C61
4K7
3
C45
100n
2C5
8
100n
2C
3
2
2C66
470p
100n 2V02
+1V2_ S W
+1V2_CORE
100n
2C50
2C42 100n
2C
3
5
100n
2C4
3
22
u
6.
3
V
2C41
22
u
6.
3
V
+ 3 V 3 _ S W
33 R
5C11
+1V2_PLL
+1V2_PLL
100n
2C71
IC1 3
100n
2C
83
MD7
A10
MD 8
B10
MD9
C10
MVREF
E 3
RA S _
J2
V S
P17
WE_
K1
MD2 8
C1
MD29
C2
MD 3
D12
MD 3 0
C 3
MD 3 1
D 3
MD4
C11
MD5
B11
MD6
A11
MD20
D6
MD21
A5
MD22
B5
MD2 3
A4
MD24
C5
MD25
A 3
MD26
A2
MD27
A1
MD1 3
B 8
MD14
C 8
MD15
D 8
MD16
D7
MD17
C7
MD1 8
B7
MD19
A7
MD2
A1 3
MA9
F 3
MCK0
D1
MCK0_
E1
MD0
C1 3
MD1
B1 3
MD10
D10
MD11
D9
MD12
A 8
MA11
F1
MA2
H2
MA 3
H1
MA4
G1
MA5
G2
MA6
G 3
MA7
G4
MA 8
F4
DQ S 0
B12
DQ S 1
B9
DQ S 2
B6
DQ S3
B2
H S
P19
MA0
H4
MA1
H 3
MA10
F2
DPB_CLK
T19
DPB_DE
W20
DPB_H S
V19
DPB_V S
V20
DQM0
A12
DQM1
A9
DQM2
A6
DQM 3
B1
DPB10
T17
DPB11
T1 8
DPB12
T20
DPB1 3
U20
DPB14
U19
DPB15
U1 8
DPB 8
R20
DPB9
R19
DPA6
V17
DPA7
U17
DPA 8
U16
DPA9
V16
DPA_CLK
Y15
DPA_H S
Y19
DPA_V S
Y20
DPA2
W1 8
DPA20
W1 3
DPA21
V1 3
DPA22
U1 3
DPA2 3
Y12
DPA 3
Y1 8
DPA4
Y17
DPA5
W17
DPA12
W15
DPA1 3
V15
DPA14
U15
DPA15
U14
DPA16
V14
DPA17
W14
DPA1 8
Y14
DPA19
Y1 3
CA S _
J1
CLKE
K2
C S 0_
J4
C S 1_
J 3
DPA0
W19
DPA1
V1 8
DPA10
W16
DPA11
Y16
7C01-2
S VP WX6 8
BA0
K 3
BA1
K4
V SS 9
H11
V SS R1
E4
V SS R2
E7
+ 3 V 3 _ S W
+1V2_CORE
V SS 42
N1 3
V SS 4 3
P1 8
V SS 44
T16
V SS 45
H20
V SS 5
D2
V SS 6
H 8
V SS 7
H9
V SS8
H10
V SS3 5
M12
V SS3 6
M1 3
V SS3 7
N 8
V SS38
N9
V SS3 9
N10
V SS 4
C12
V SS 40
N11
V SS 41
N12
V SS 2 8
L11
V SS 29
L12
V SS3
C9
V SS3 0
L1 3
V SS3 1
M 8
V SS3 2
M9
V SS33
M10
V SS3 4
M11
V SS 20
K10
V SS 21
K11
V SS 22
K12
V SS 2 3
K1 3
V SS 24
L5
V SS 25
L 8
V SS 26
L9
V SS 27
L10
V SS 1 3
J9
V SS 14
J10
V SS 15
J11
V SS 16
J12
V SS 17
J1 3
V SS 1 8
K 8
V SS 19
K9
V SS 2
C6
VREFN_1
V5
VREFN_2
V7
VREFP_1
W5
VREFP_2
W7
V SS 1
B 3
V SS 10
H12
V SS 11
H1 3
V SS 12
J 8
VDDM4
D5
VDDM5
D11
VDDM6
E5
VDDM7
E6
VDDM 8
E9
VDDM9
E10
VDDR1
E2
VDDR2
E 8
VDDH 8
R1 8
VDDM1
B4
VDDM10
E11
VDDM11
E12
VDDM12
F5
VDDM1 3
G5
VDDM2
C4
VDDM 3
D4
VDDC9
G16
VDDH1
L16
VDDH2
M16
VDDH 3
N16
VDDH4
P16
VDDH5
T12
VDDH6
T1 3
VDDH7
R17
VDDC1 8
T15
VDDC2
C15
VDDC 3
D1 3
VDDC4
D14
VDDC5
D15
VDDC6
E1 3
VDDC7
E14
VDDC 8
E15
VDDC10
H5
VDDC11
H16
VDDC12
J5
VDDC1 3
J16
VDDC14
K5
VDDC15
K16
VDDC16
R16
VDDC17
T14
LVD S _V SS O 2
C19
LVD S _V SS P
E1 8
NC
P20
PAVDD1
T 3
PAVDD2
T4
PAV SS 1
T2
PAV SS 2
R 3
VDDC1
C14
LVD S _VDD A
E17
LVD S _VDD D
D16
LVD S _VDDO1
C17
LVD S _VDDO2
D17
LVD S _VDD P
D1 8
LVD S _V SS A
E16
LVD S _V SS D
C16
LVD S _V SS O 1
C1 8
V1
AV SS LLPLL
T1
AV SS _ADC1
T5
AV SS _ADC2
T7
AV SS _ADC 3
T9
AV SS _ADC4
T6
AV SS _BG_A SS
W 3
AV SS _OUTBUF
Y2 V 3
AVDD 3 _OUTBUF
U 3
AVDDAPLL
U1
AVDDLLPLL
R2
AVDD_ADC1
U5
AVDD_ADC2
U7
AVDD_ADC 3
T 8
AVDD_ADC4
U6
AV SS APLL
7C01-4
S VP WX6 8
AVDD 3 _ADC1
Y 3
AVDD 3 _ADC2
U9
AVDD 3 _BG_A SS
100n
2C77
2C67
10
u
6.
3
V
2C7
8
10
u
6.
3
V
3 C4 8
22R
3 C46
22R
33 R
5C1 8
2C
3
6
10
u
6.
3
V
33 R
5C14
100n
2C
3
7
100n
2C40
100n
2C
3
9
33 R
5C17
100n
2C57
2C62
10
u
6.
3
V
2C60
10
u
6.
3
V
100n
2C59 2C16
DDR_VREF
100n
100n
2C47
100n
2C55
100n
2C51
100n
2V01
100n
2C5
3
2C44
100n
100n
2C4
8
100n
2C52
+ 3 V 3 _ S W
+1V2_PLL
33 R
5C10
33 R
5C09
100p 2C 8 9
100n
2C6
8
100p 2C 8 5
+ 3 V 3 _ S W
100n
2C75
22R
3 C 33
10
u
6.
3
V
IC01
2C72
33 R
5C1 3
+1V2_ADC
33 R
5C16
+1V2_ADC
+1V2_ADC
+ 3 V 3 _ S W
FC02
33 R
5C15
33 R
5C22
33 R
5C21
33 R
5C20
6.
3
V
2C
8
0
10
u
100n
2C
3
1
2C99
10
u
6.
3
V6
.
3
V
100n
2C6
3
2C95
10
u
2C9
3
10
u
6.
3
V
100n
2C79
100n 2V0
3
100n
2C9
8
100n
2C49
100n
2C94
100n 2C92
100n
2C90 2C91
10
u
6.
3
V
+2V5_VDDMQ
+5V_ S W
+ 3 V 3 _ S W
100n
2C 33
100p 2C 8 7
100p 2C 8 4
100p 2C 88
100p 2C 8 6
22R
3 C 3 7
IC02
2C70
10
u
6.
3
V
3 C 3 0
9
71
4
8
22R
7C0 3 -4
74LCX14T
33 R
5C12
+ 3 V 3 _ S W
+ 3 V 3 _ S W
2C64
10
u
6.
3
V
2C97
10
u
6.
3
V
14
12
100n 2C96
74LCX14T
7C0 3 -6
1 3
7
11
71
4
10
74LCX14T
7C0 3 -5
+ 3 V 3 _ S W
+5V_ S W
3 C 3 1
22R
3 C 3 6
22R
5
71
4
6
1
71
4
2
7C0 3 - 3
74LCX14T
7C0 3 -1
74LCX14T
3 C07
100R
FC0 3
FC01
4K7
3 C22
100R
2C27
3 C09
10
u
6.
3
V
4K7
3
C29
3
C
3
2
4K7
2C0 3
100n
3 C 3 4
22R
74LCX14T
3
71
4
4
7C0 3 -2
FPGA_BL_DIMMING
3 C25 10K
4C0 8
100R
3 C24
2C7 3
10 u
1 8 p 2C02
+ 3 V 3 _ S W
4K7
3
C44
2C29
10
u
6.
3
V
4K7
3
C41
100n
2C17
100n 2C11
100n 2C10
100n 2C09
100n 2C07
+ 3 V 3 _ S TBY
100n
2C22
IC1 8
6.
3
V
33 R
2C2
3
10
u
5C07
100n 2C19
4K7
3
C42
4K7
3
C40
1 8
4K7
3
C
3
9
3 C06-1 100R
100R 1 8
5
3 C05-1
100R 3 C04-4 4
100R 3 6
100R 1 8
+ 3 V 3 _ S W
3 C04- 3
3 C04-1
BC 8 47BW
7C02
7C04
220R
3 C2 3
BC 8 47BW
1C24
24M0
100n
2C20
3 C20 1K0
+ 3 V 3 _ S W
+ 3 V 3 _ S W
100R 3 C0 8
+ 3 V 3 _ S W
3 C0 3 -2 2
7
4 5
100R
3 C0 3 -4 100R
3
C4
3
4K7
100R
3 C06- 3 3
6
100R
4 5
3 C06-4
33 R
5C06
22 u
2C74
100n 2C1 8
100n 2C15
3 6
100n 2C0 8
3 C05- 3
100R
100n 2C06
100n 2C05
100n
W6
Y_G 3
Y6
+ 3 V 3 _ S W
2C04
S DA
H17
TE S TMODE
F17
V5 S F
F16
WR_
J19
XTALI
W1
XTALO
Y1
Y_G1
V6
Y_G2
PLF2
R4
PR_R1
Y 8
PR_R2
W 8
PR_R 3
V 8
PWM0
G17
RD_
J20
RE S ET
F1 8
S CL
H1 8
INTN
G1 8
MLF1
U2
PB_B1
W9
PB_B2
Y9
PB_B 3
Y10
PC_B
W10
PC_G
Y7
PC_R
U 8
CPU_C S
J17
CVB S 1
Y4
CVB S _OUT1
W2
CVB S _OUT2
V2
Y5
FB1
FB2
U4
F S 1
V4
F S 2
W4
ADDR4
M20
ADDR5
M19
ADDR6
M1 8
ADDR7
M17
V10
AIN_H
AIN_V
U10
ALE
J1 8
C
V9
AD4
K17
AD5
K1 8
AD6
K19
AD7
K20
N17
ADDR0
ADDR1
N1 8
ADDR2
N19
ADDR 3
N20
7C01-1
S VP WX6 8
L17
AD0
AD1
L1 8
AD2
L19
AD 3
L20
IC07
100n
2C25
100n
2C24
2C2
8
100n
IC16
2n7 2C 8 2
33 R
IC17
5C0 8
IXXX
100R
2 7
4 5
3 C06-2
100R 3 C05-4
2 7
3 C04-2 100R
100n
2C1 3
470R
4C07
3 C19
3 6
IXXX
IXXX
3 C0 3 - 3 100R
2n7 2C 8 1
2 7
3 C05-2
100R
100n 2C12
IXXX
IXXX
1 8 p 2C01
3
C01
1M0
+ 3 V 3 _ S W
100n
2C26
2C
3
01
0
0
n
IC14 IC15
3 C02
33 R
IXXX
P 3
TMD S _GND4
TMD S _GND5
R1
W S
U12
IXXX
TD2P
F20
TE1M
B19
TE1P
A19
TE2M
H19
TE2P
G20
TMD S _GND1
L 3
TMD S _GND2
M 3
TMD S _GND 3
N 3
TC2P
D20
TCLK1M
B17
TCLK1P
A17
TCLK2M
F19
TCLK2P
E20
TD1M
B1 8
TD1P
A1 8
TD2M
G19
TA2P
A20
TB1M
B15
TB1P
A15
TB2M
D19
TB2P
C20
TC1M
B16
TC1P
A16
TC2M
E19
L2
S CDT
V11
S CK
Y11
S D0
V12
S PDIF
W12
TA1M
B14
TA1P
A14
TA2M
B20
R5
RX0+
M1
RX0-
M2
RX1+
N1
N2
RX1-
RX2+
P1
RX2-
P2
RXC+
L1
RXC-
N4
AVCC 3
N5
AVCC4
P4
DGND
P5
D S CL
T11
D S DA
U11
L4
PVCC
PWR5V
T10
REGVCC
7C01- 3
ANT S TO
M5
AUDIOCLK
W11
M4
AVCC1
AVCC2
S VP WX6 8
IXXX
100R
1 8
3 C0 3 -1
100n
2C21
3 C10
IXXX
22R
BL_ADJU S T_PWM
CVB S _IN_DTV
S C1_G_IN
DP_H S
WX_WE#
WX_MD4
WX_MD5
WX_MD6
WX_MD7
WX_MD 8
WX_MD9
WX_RA S #
WX_MD2 3
WX_MD24
WX_MD25
WX_MD26
WX_MD27
WX_MD2 8
WX_MD29
WX_MD 3
WX_MD 3 0
WX_MD 3 1
WX_MD14
WX_MD15
WX_MD16
WX_MD17
WX_MD1 8
WX_MD19
WX_MD2
WX_MD20
WX_MD21
WX_MD22
WX_MA9
WX_MCK0
WX_MCK0#
WX_MD0
WX_MD1
WX_MD10
WX_MD11
WX_MD12
WX_MD1 3
WX_MA0
WX_MA1
WX_MA10
WX_MA11
WX_MA2
WX_MA 3
WX_MA4
WX_MA5
WX_MA6
WX_MA7
WX_MA 8
WX_DQM0
WX_DQM1
WX_DQM2
WX_DQM 3
WX_DQ S 0
WX_DQ S 1
WX_DQ S 2
WX_DQ S3
DP_H S
HDMI_H
HDMI_V
HDMI_Cr(0)
HDMI_Cr(1)
HDMI_C b (0)
HDMI_C b (1)
HDMI_Y(0)
HDMI_Y(1)
HDMI_DE
HDMI_Cr( 8 )
HDMI_Cr(9)
HDMI_Y(5)
HDMI_Y(6)
HDMI_Y(7)
HDMI_Y( 8 )
HDMI_Y(9)
HDMI_C b (2)
HDMI_C b ( 3 )
HDMI_VCLK
HDMI_C b (6)
HDMI_C b (7)
HDMI_C b ( 8 )
HDMI_C b (9)
HDMI_Cr(2)
HDMI_Cr( 3 )
HDMI_Cr(4)
HDMI_Cr(5)
HDMI_Y(4)
HDMI_Cr(6)
HDMI_Cr(7)
WX_BA0
WX_BA1
WX_CA S #
WX_CLKE
WX_C S 0#
HDMI_Y(2)
HDMI_Y( 3 )
HDMI_C b (4)
HDMI_C b (5)
WX_AV SS _ADC1
WX_AV SS _ADC2
WX_LVD S _V SS
WX_LVD S _VD D
WX_AVDD 3 _ADC1
WX_AVDD 3 _ADC2
WX_AVDD_ADC4
WX_AV SS APLL
WX_AVDDAPLL
WX_AV SS LLPLL
WX_AVDDLLPLL
WX_PAV SS 2
WX_PAVDD 2
WX_AV SS _ADC1
WX_AVDD_ADC1
WX_AV SS _ADC2
WX_AVDD_ADC2
WX_AV SS _ADC 3
WX_AVDD_ADC 3
WX_AV SS _ADC4
WX_AV SS _OUTBUF
WX_AVDD 3 _OUTBUF
WX_AV SS _BG_A SS
WX_AVDD 3 _BG_A SS
WX_PAV SS 1
WX_PAVDD 1
WX_AV SS _ADC4
WX_AV SS _BG_A SS
WX_AV SS _OUTBUF
WX_LVD S _VD D
WX_LVD S _V SS
WX_PAVDD 1
WX_PAVDD 2
WX_PAV SS 1
WX_PAV SS 2
WX_AVDD 3 _ADC1
WX_AVDD 3 _ADC2
WX_AVDD 3 _BG_A SS
WX_AVDD 3 _OUTBUF
WX_AVDDAPLL
WX_AVDDLLPLL
WX_AVDD_ADC1
WX_AVDD_ADC2
WX_AVDD_ADC
3
WX_AVDD_ADC4
WX_AV SS APLL
WX_AV SS LLPLL
WX_AV SS _ADC1
WX_AV SS _ADC2
WX_AV SS _ADC 3
WX_PAVDD 1
WX_PAVDD 2
PC_VGA_H
PC_VGA_V
VGA_H
VGA_V
BL_ADJU S T_ANA
WX_REGVCC
VGA_G_IN
VGA_B_IN
WX_PVCC
WX_AVCC
S C1_B_IN
S C1_CVB S _IN
HD_PR_IN
S C2_C_IN
S C1_R_IN
VGA_R_IN
CVB S _RF
HD_Y_IN
S C2_Y_CVB S _IN
S VH S _Y_CVB S _IN
S VH S _C_IN
HD_PB_IN
IIC_ S CL_ S IDE
IIC_ S DA_ S IDE
C S
S VPWX_R S T
A(5)
A(6)
A(7)
A(0:7)
AD(0:7)
A(0)
A(1)
A(2)
A(
3 )
A(4)
AD(5)
AD(6)
AD(7)
AD(0)
AD(1)
AD(2)
AD(
3 )
AD(4)
RD
WR
S C1_RF_OUT_CVB S
S C2_CVB S _MON_OUT
S C1_FBL_IN
S VPWX_INT
PC_VGA_H
PC_VGA_V
ALE_EMU
TxFPGAe_4p
TxFPGAe_4n
TxFPGAo_4n
TxFPGAo_4p
TxFPGAe_CLKp
WX_AVCC
WX_PVCC
WX_REGVCC
TxFPGAe_2n
TxFPGAe_2p
TxFPGAe_ 3 n
TxFPGAe_ 3 p
TxFPGAe_CLKn
TxFPGAo_CLKp
TxFPGAe_0n
TxFPGAe_0p
TxFPGAe_1n
TxFPGAe_1p
TxFPGAo_2p
TxFPGAo_ 3 n
TxFPGAo_ 3 p
TxFPGAo_CLKn
TxFPGAo_0n
TxFPGAo_0p
TxFPGAo_1n
TxFPGAo_1p
TxFPGAo_2n
B04A B04A
I_17760_005.ep s
1 8 020 8
3 1 3 9 12 3 6 3 49.1