IC Data Sheets
8.
Figure 8-9 Pin configuration
19490_
3
0
8
_1
3
041
3
.ep
s
1
3
041
3
Pinnin
g
information
PNX5
8
XXX [7/16]
K26
CA_DATA_EN
O
CMO
S
3
.
3
V, PD
CA D
a
t
a
B
us
En
ab
le
L1
M0_A
8
O
DDR2
a
ddr
Memory Addre
ss
b
it
8
L2
M0_A6
O
DDR2
a
ddr
Memory Addre
ss
b
it 6
L
3
M0_A4
O
DDR2
a
ddr
Memory Addre
ss
b
it 4
L4
V
SS
PWR gro
u
nd
L5
M0_C
S
B
O
DDR2
a
ddr
Memory Chip
S
elect
L6
VDD_1V
8
PWR
su
pply
L7
VDD_1V
8
PWR
su
pply
L9
VDD_1V15
PWR
su
pply
L11
VDD_1V15
PWR
su
pply
L1
3
VDD_1V15
PWR
su
pply
L15
VDD_1V15
PWR
su
pply
L17
VDD_1V15
PWR
su
pply
L20
V
SS
PWR gro
u
nd
L21
CA_MDO7
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t
b
it 7
L22
CA_MO
S
TRT
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t P
a
cket
S
t
a
rt
L2
3
CA_MOVAL
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t P
a
cket V
a
lid
L24
CA_RDY
I
CMO
S
3
.
3
V, PD
CA Re
a
dy
L25
CA_MCLKO
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t Clock
L26
CA_R
S
T
O
CMO
S
3
.
3
V, PD
CA Re
s
et to PCMCIA Mod
u
le
M1
M0_PCAL
I/O
DDR2 d
a
t
a
Preci
s
ion C
a
li
b
r
a
tion Re
s
i
s
tor
M2
M0_A1
3
O
DDR2
a
ddr
Memory Addre
ss
b
it 1
3
M
3
M0_A11
O
DDR2
a
ddr
Memory Addre
ss
b
it 11
M4
M0_ODT
O
DDR2
a
ddr
Memory On-Die Termin
a
tion
M5
M0_RA
S
B
O
DDR2
a
ddr
Memory Row Addre
ss
S
tro
b
e
M6
V
SS
PWR gro
u
nd
M7
V
SS
PWR gro
u
nd
M10
V
SS
PWR gro
u
nd
M12
V
SS
PWR gro
u
nd
M14
V
SS
PWR gro
u
nd
M16
V
SS
PWR gro
u
nd
M1
8
V
SS
PWR gro
u
nd
M20
VDD_
3
V
3
PWR
su
pply
M21
CA_MDO1
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t
b
it 1
M22
CA_MDO2
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t
b
it 2
M2
3
CA_MDO
3
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t
b
it
3
M24
CA_MDO4
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t
b
it 4
M25
CA_MDO5
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t
b
it 5
M26
CA_MDO6
I
CMO
S
3
.
3
V, 5 VT, PD
CA Tr
a
n
s
port
S
tre
a
m Inp
u
t
b
it 6
B
a
ll
S
ym
b
ol
P
a
d
direc-
tion
P
a
d type
De
s
cription