Philips 26HFL5008D/12, Руководство по обслуживанию

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IC Data Sheets EN 40 Q552.5HE LA 8.
2013-Sep-20
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div. table
Figure 8-8 Pin configuration
19490_ 3 07_1 3 041 3 .ep s
1 3 041 3
Pinnin g information
PNX5 8 XXX [6/16]
H25 CA_A6 O CMO S 3 . 3 V CA Addr B us Bit-6 (O u tp u t)
H26 CA_A7 O CMO S 3 . 3 V CA Addr B us Bit-7 (O u tp u t)
J1 M0_A0 O DDR2 a ddr Memory Addre ss b it 0
J2 M0_A10 O DDR2 a ddr Memory Addre ss b it 10
J 3 M0_A1 O DDR2 a ddr Memory Addre ss b it 1
J4 M0_A12 O DDR2 a ddr Memory Addre ss b it 12
J5 M0_A9 O DDR2 a ddr Memory Addre ss b it 9
J6 VDD_1V15 PWR su pply
J7 VDD_1V15_DDR PWR su pply DDR PLL su pply
J9 VDD_1V15 PWR su pply
J11 VDD_1V15 PWR su pply
J1 3 VDD_1V15 PWR su pply
J15 VDD_1V15 PWR su pply
J17 VDD_1V15 PWR su pply
J20 V SS PWR gro u nd
J21 CA_OOB_EN O CMO S 3 . 3 V, PD CA O u t of B a nd En ab le
J22 CA_ADD_EN O CMO S 3 . 3 V, PD CA Addre ss B us En ab le
J2 3 CA_VCCEN O CMO S 3 . 3 V, PD CA PCMCIA Mod u le Power En ab le
J24 CA_VPPEN O CMO S 3 . 3 V, PD CA PCMCIA Mod u le Power En ab le
J25 CA_A0 O CMO S 3 . 3 V CA Addr B us Bit-0 (O u tp u t)
J26 CA_A1 O CMO S 3 . 3 V CA Addr B us Bit-1 (O u tp u t)
K1 M0_A2 O DDR2 a ddr Memory Addre ss b it 2
K2 V SS PWR gro u nd
K 3 M0_CA S B O DDR2 a ddr Memory Col u mn Addre ss S tro b e
K4 M0_CKE O DDR2 a ddr Memory Clock En ab le
K5 M0_A14 O DDR2 a ddr Memory Addre ss b it 14
K6 V SS PWR gro u nd
K7 V SS PWR gro u nd
K10 V SS PWR gro u nd
K12 V SS PWR gro u nd
K14 V SS PWR gro u nd
K16 V SS PWR gro u nd
K1 8 V SS PWR gro u nd
K20 VDD_ 3 V 3 PWR su pply
K21 CA_CDN0 I CMO S 3 . 3 V, 5 VT, PD CA C a rd Detect b it 0
K22 CA_CDN1 I CMO S 3 . 3 V, 5 VT, PD CA C a rd Detect b it 1
K2 3 CA_V S N0 I CMO S 3 . 3 V, 5 VT, PD CA PCMCIA Volt a ge S en s e b it 0
K24 CA_V S N1 I CMO S 3 . 3 V, 5 VT, PD CA PCMCIA Volt a ge S en s e b it 1
K25 CA_DATA_DIR O CMO S 3 . 3 V, PD CA D a t a B us Direction
B a ll S ym b ol P a d
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