Current DRAM Frequency
This item displays the memory (DRAM) frequency. This is a
display-only item. You cannot make changes to this field.
DRAM Clock (100 MHz)
This item enables you to manually set the DRAM Clock. We
recommend that you leave this item at the default value.
DRAM Timing (Manual)
Set this to the default value to enable the system to automatically
set the SDRAM timing by SPD (Serial Presence Detect). SPD is an
EEPROM chip on the DIMM module that stores information about
the memory chips it contains, including size, speed, voltage, row
and column addresses, and manufacturer. If you disable this item,
you can use the following three items to manually set the timing
parameters for the system memory
DRAM CAS Latency (2.5)
Enables you to select the CAS latency time in HCLKs of 2/2 or 3/3.
The value is set at the factory depending on the DRAM installed.
Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU. The
options are "2" and "2.5" default.
Bank Interleave (Disabled)
Enable this item to increase memory speed. When enabled,
separate memory banks are set for odd and even addresses and the
next byte of memory can be accessed while the current byte is
being refreshed.
Precharge to Active (3T/4T)
This item is used to designate the minimum Row Precharge time of
the SDRAM devices on the module.
DRAM must continually be refreshed or it will lose its data.
Normally, DRAM is refreshed entirely as the result of a single
request. This option allows you to determine the number of CPU
clocks allocated for the Row Address Strobe (RAS) to accumulate
its charge before the DRAM is refreshed. If insufficient time is
allowed, refresh may be incomplete and data lost.
Active to Precharge (6T/10T)
This item specifies the number of clock cycles needed after a bank
active command before a precharge can occur.
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