7.
Circuit Diagrams and PWB Layouts
SSB: EPLD
COM
OUT
IN
VCCA
GNDA
GNDG
GND
PLL2
BANK1
PLL2
PLL1
PLL1
VCCIO
PLL1
PLL2
BANK2
BANK3
BANK4
VCCINT
DEV_OE
DEV_CLR
0
6
0
6
TA
TB
TC
TD
CLKIN
TCLK
+
-
VCC
GND
LVDS GND
PLL GND
LVDS VCC
PLL VCC
TA
+
-
-
+
-
+
-
+
R|F
PDWN
RS
TB
TC
TD
0
6
0
6
LVDS TRANSMITTER
EPLD
LVDS OUT
EAGLE INTERFACE
FOR LCD ONLY
(NC)
(NC)
FROM DC-DC CONVERTER
TO PLASMA PANEL (TIMING CONTROL)
FROM SCALER INTERFACE
FROM EPLD
TO LCD PANEL (TIMING CONTROL)
NC
(1G50)
FOR MFD ONLY
FOR UFD ONLY
N.C.
N.C.
(H=NORMAL)
*
*
B20
RES
RES
7N02-6 A8
7P01 B2
7P02 D7
FP01 A1
FP02 A4
FP03 B2
FP04 B3
FP05 C4
FP06 D4
FP07 E4
FP08 E4
FP09 E4
FP10 F4
FP11 F4
FP12 F4
FP13 F4
FP14 G4
FP15 D11
FP16 D11
FP17 E11
2P36 D8
2P37 E8
2P38 E8
2P39 E8
2P40 F8
2P41 F8
2P42 F8
2P43 F8
2P44 G8
2P45 G8
3P01 D5
3P03 E5
3P04 D9
3P05 D9
4P01 F10
4P02 F10
4P03 F10
4P04 F10
4P05 F10
4P06 F10
4P07 F10
4P08 F10
4P09 D9
4P10 E9
5P01 A3
5P02 B3
5P03 C3
5P04 D6
5P05 D6
5P06 D7
7N02-3 A6
7N02-4 E2
2P04 B3
2P05 B3
2P06 B3
2P07 B4
2P08 B4
2P09 B4
2P10 B4
2P11 B4
2P12 B4
2P13 B4
2P14 B5
2P15 B1
2P16 B1
2P17 B2
2P18 B3
2P19 B3
2P20 B3
2P21 B3
2P22 C3
2P23 C3
2P24 C3
2P25 C3
2P26 C3
2P27 C3
2P28 C4
2P29 C4
2P30 C4
2P31 C5
2P32 D5
2P33 D5
2P34 D6
2P35 D7
7
8
9
10
11
A
B
C
D
E
F
G
A
B
C
D
E
F
G
1P01 E8
1P02 E8
1P03 F8
1P04 F8
1P05 G8
1P06 A11
1P07 D11
2P01 B3
2P02 B3
2P03 B3
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
1P07
+3V3SW
+3V3-IO
FI-WE31P-HFE-E1500
5
6
+3V3SW
4P10
+3V3SW
4P09
+3V3SW
4P07
4P08
+3V3SW
4P06
+3V3SW
4P05
4P04
4P03
3P04
100R
100R
3P05
LVDS_VCC
29
3
30
4
5
6
7
8
9
31
32
20
21
22
23
24
25
26
27
28
10
11
12
13
14
15
16
17
18
19
2
1P06
0-1453230-3
1
4P02
+3V3SW
4P01
LVDS_VCC
FP16
FP17
FP15
6
7
8
9
32
33
24
25
26
27
28
29
3
30
31
4
5
14
15
16
17
18
19
2
20
21
22
23
1
10
11
12
13
1
2
4
3
1
2
4
3
1P05
DLW21S
DLW21S
1P01
47R
3P03
FP06
FP07
FP13
FP14
FP12
FP10
FP11
FP09
FP08
5P05
5P06
5P04
1
2
4
3
1
2
4
3
DLW21S
1P04
3
1P03
DLW21S
1
2
4
DLW21S
1P02
10p
2P36
2P37 10p
10p
2P44
10p
2P45
10p
2P42
2P43 10p
2P40
10p
10p
2P41
10p
2P38
2P39
10p
2P34 100n
100n
2P31
2P35
100n
100n
2P33
100n
3P01
2P32
4K7
16
18
25
9
26
28
30
39
40
37
38
50
2
8
10
12
14
15
19
41
42
20
22
23
24
27
54
55
56
3
4
45
46
6
7
11
44
32
33
35
34
1
17
47
48
51
52
31
5
13
21
29
53
36
43
49
IO_99
M13
THC63LVDM83R
7P02
IO_93
N15
IO_94
N16
IO_95
K12
IO_96
K14
IO_97
L12
IO_98
N14
IO_129
C15
IO_130
C14
IO_131
D13
IO_89
N13
IO_90
P14
IO_91
P15
IO_92
R16
D15
IO_122
E14
IO_123
F12
IO_124
E13
IO_125
D14
IO_126
H13
IO_127
G12
IO_128
B16
IO_114
F16
IO_115
F14
IO_116
F13
IO_117
F15
IO_118
E16
IO_119
E15
IO_120
D16
IO_121
L16
IO_107
K16
IO_108
K15
IO_109
J16
IO_110
H12
IO_111
G14
IO_112
G13
IO_113
G15
IO_100
M14
IO_101
L13
IO_102
M15
IO_103
M16
IO_104
L14
IO_105
L15
IO_106
IO_179
B2
BANK 3
Φ
7N02-4
EP1C12F256C8
IO_171
E5
IO_172
C5
IO_173
B5
IO_174
A4
IO_175
B4
IO_176
C4
IO_177
B3
IO_178
A2
B7
IO_164
A6
IO_165
E7
IO_166
B6
IO_167
C6
IO_168
D6
IO_169
D5
IO_170
E6
E10
IO_156
C8
IO_157
D8
IO_158
E8
IO_159
A8
IO_160
B8
IO_161
D7
IO_162
C7
IO_163
A11
IO_148
B10
IO_149
C10
IO_150
D10
IO_151
A9
IO_152
B9
IO_153
D9
IO_154
C9
IO_155
C12
IO_140
E12
IO_141
E11
IO_142
E9
IO_143
D12
IO_144
D11
IO_145
C11
IO_146
B11
IO_147
IO_132
B15
IO_133
A15
IO_134
B14
IO_135
C13
IO_136
B13
IO_137
A13
IO_138
B12
IO_139
Φ
BANK 2
EP1C12F256C8
7N02-3
A3
P16
K11
C16
T3
L7
L10
T14
+3V3-IO
H9
J8
J10
K7
C1
G6
P1
A14
F10
F7
H6
H11
A7
K9
T7
T10
A10
G8
G10
H7
A5
A12
F6
F8
F9
F11
G7
J6
J11
J5
J12
K10
L6
A16
L8
L9
L11
T1
T5
T12
T16
POWER
A1
G9
G11
H8
H10
J7
J9
K6
K8
Φ
7N02-6
EP1C12F256C8
+3V3SW
+1V5-PLL
+1V5-INT
FP03
+1V5
FP01
2u2
2P17
3
100n
2P16
7P01
LF15ABDT
2
1
2P15
100u
16V
2P14
100n
100n
2P12
2P13
100n
5P01
5P03
5P02
2P19
100n
100n
2P20
2P23
100n
100n
2P24
2P25
100n
100n
2P26
100n
100n
2P02
2P03
100n
2P04
2P05
100n
FP04
+1V5-PLL
2P18
2u2
100n
2P21
FP02
2P11
100n
FP05
100n
2P10
2P09
100n
100n
2P08
2P07
100n
+3V3-IO
+1V5-INT
2u2
2P01
100n
2P30
2P29
100n
100n
2P28
2P27
100n
2P22
2u2
100n
2P06
SCL_DMA_BUS1_DISP
SDA_DMA_BUS1_DISP
VDISP2
VDISP_2
CTRL_DISP1
CTRL_DISP2
LVDS_OPT
LVDS_OPT
LVDSA-
LVDSA+
LVDSB-
LVDSB+
LVDSC-
LVDSC+
LVDSCLK-
LVDSD-
LVDSD+
CLK_OUT
LVDSBp
LVDSB-
LVDSBn
LVDSC+
LVDSCp
LVDSC-
LVDSCn
LVDSDp
LVDSD+
LVDSDn
LVDSD-
DE_OUT
R(6)
R(3)
R(4)
R(7)
R(5)
G(0)
G(1)
G(2)
LVDSAp
LVDSA+
LVDSAn
LVDSA-
LVDSB+
G(4)
G(5)
B(0)
B(6)
B(7)
B(1)
B(2)
R(2)
B(3)
B(4)
B(5)
PARITY_OUT
HS_OUT
VS_OUT
LVDS_PWR_DWN
LVDSCLKp
LVDSCLKn
LVDSCLK-
R(0)
R(1)
G(6)
G(7)
G(3)
R(5)
G(6)
R(6)
B(6)
G(2)
G(1)
B(4)
B(5)
B(2)
B(3)
PARITY_OUT
HS_OUT
B(7)
B(0)
CLK_OUT
G(7)
G(3)
G(4)
G(5)
B(1)
VS_OUT
DE_OUT
R(0)
R(1)
R(2)
R(3)
R(4)
G(0)
R(7)
B21
B21
3139 123 6093.1
F_15270_031.eps
250505
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